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| ASAHI KASEI [AK4632] 16-Bit Mono CODEC with ALC & MIC/SPK/Video-AMP GENERAL DESCRIPTION The AK4632 is a 16-bit mono CODEC with Microphone-Amplifier, Speaker-Amplifier and VideoAmplifier. Input circuits include a Microphone-Amplifier and an ALC (Automatic Level Control) circuit. Output circuits include a Speaker-Amplifier and Mono Line Output. Video circuits include a LPF and Video-Amplifier. The AK4632 suits a moving picture of Digital Still Camera and etc. This speaker-Amplifier supports a Piezo Speaker. The AK4632 is housed in a space-saving 32-pin QFN package. FEATURE 16-Bit Delta-Sigma Mono CODEC Recording Function * 1ch Mono Input * 1st MIC Amplifier: 0dB, 20dB, 26dB or 32dB * 2nd Amplifier with ALC: -8dB +27.5dB, 0.5dB Step * ADC Performance: S/(N+D): 80dB, DR, S/N: 85dB Playback Function * Digital Volume: +12dB -115dB, 0.5dB Step, Mute * Mono Line Output Performance: S/(N+D): 85dB, S/N: 93dB * Mono Speaker-Amp - Speaker-Amp Performance: S/(N+D): 60dB, S/N: 90dB (150mW@ 8) - BTL Output - ALC (Automatic Level Control) Circuit - Output Power: 400mW @ 8, SVDD=3.3V 3.0Vrms@SVDD=5V * Beep Input Power Management Video Function * A Composite Video Input * Gain Control (-1.0dB +10.5dB, 0.5dB Step) * Low Pass Filter * A Video-Amp for Composite Video Signal(+6dB) * DC Direct Output or Sag Compensation Output Flexible PLL Mode: * Frequencies: 11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin) 1fs (FCK pin) 16fs, 32fs or 64fs (BICK pin) EXT Mode: * Frequencies: 256fs, 512fs or 1024fs (MCKI pin) Sampling Rate: * PLL Slave Mode (FCK pin) : 7.35kHz ~ 26kHz * PLL Slave Mode (BICK pin) : 7.35kHz ~ 48kHz * PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz * PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz AK4632 1. 2. 3. 4. 5. 6. 7. 8. MS0396-E-00 -1- 2005/06 ASAHI KASEI [AK4632] * EXT Slave Mode: 7.35kHz ~ 48kHz (256fs), 7.35kHz ~ 26kHz (512fs), 7.35kHz ~ 13kHz (1024fs) 9. Output Master Clock Frequency: 256fs 10. Serial P Interface: 3-wire 11. Master / Slave Mode 12. Audio Interface Format: MSB First, 2's compliment * ADC: DSP Mode, 16bit MSB justified, I2S * DAC: DSP Mode, 16bit MSB justified, 16bit LSB justified, I2S 13. Ta = -10 70C 14. Power Supply * CODEC: 2.6 3.6V (typ. 3.3V) * Speaker-Amp: 2.6 5.25V (typ. 3.3V/5.0V) * Video-Amp: 2.8 5.25V (typ. 3.3V/5.0V) 15. Power Supply Current: 23.5 mA (All Power ON) 16. Package: 32pin QFN 17. Register Compatible with AK4631 Block Diagram VCOM MICOUT MPI MIC MIC-AMP 0dB or 20dB or 26dB or 32dB PMMIC MIC Power Supply ALC1 (IPGA) PMADC AVSS AVDD AIN DVDD DVSS PDN ADC HPF PMAO ALC1A DACA PMDAC Audio Interface DVOL FCK BICK AOUT BEEPA DACM ALC1M DAC SDTO SDTI SVDD SVSS PMSPK DSP and uP SPP SPKAMP SPN BEEP PMBP MIX ALC2 Control Register CSN CCLK CDTI PMV PMPLL MCKO VOUT +6dB -1dB ~ +10.5dB Step 0.5dB PLL MCKI VSAG VIN VVDD MIN MOUT VCOC Figure 1. AK4632 Block Diagram MS0396-E-00 -2- 2005/06 ASAHI KASEI [AK4632] Ordering Guide AK4632VN AKD4632 -10 +70C 32pin QFN (0.5mm pitch) Evaluation board for AK4632 Pin Layout MCKO SVDD 18 24 23 22 21 20 MOUT AOUT BEEP AIN MICOUT MIC MPI VCOM 19 17 DVSS SVSS MCKI SPN SPP MIN 25 26 27 28 29 30 31 32 7 1 2 3 4 5 6 8 16 15 14 DVDD BICK FCK SDTO SDTI CDTI CCLK CSN AK4632VN Top View 13 12 11 10 9 VCOC AVDD VVDD VSAG VOUT AVSS Compare with AK4632 Function Video Function Package AK4631 No 28pin QFN (5.2mm x 5.2mm) AK4632 Yes 32pin QFN (5.0mm x 5.0mm) The audio function of the AK4632 is compatible with that of the AK4631. Since the register map of audio function is the same as the AK4631's, the software of the audio function can run on the AK4632 without any change. MS0396-E-00 -3- PDN VIN 2005/06 ASAHI KASEI [AK4632] PIN/FUNCTION No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name VCOC AVDD AVSS VVDD VIN VOUT VSAG PDN CSN CCLK CDTI SDTI SDTO FCK BICK DVDD DVSS MCKI MCKO SPN SPP SVDD SVSS MIN MOUT AOUT BEEP AIN MICOUT MIC MPI VCOM I/O O I O I I I I I I O I/O I/O I O O O I O O I I O I O O Function Output Pin for Loop Filter of PLL Circuit This pin should be connected to AVSS with one resistor and capacitor in series. Analog Power Supply Pin Analog Ground Pin Video Block Power Supply Pin. Composite Video Signal Input Pin Composite Video Signal Driver Pin Composite Video Signal Output Feedback Input Pin Power-Down Mode Pin "H": Power up, "L": Power down reset and initialize the control register. Chip Select Pin Control Data Clock Pin Control Data Input Pin Audio Serial Data Input Pin Audio Serial Data Output Pin Frame Clock Pin Audio Serial Data Clock Pin Digital Power Supply Pin Digital Ground Pin External Master Clock Input Pin (Internal Pull Down 25k@PDN pin ="L") Master Clock Output Pin Speaker Amp Negative Output Pin Speaker Amp Positive Output Pin Speaker Amp Power Supply Pin Speaker Amp Ground Pin ALC2 Input Pin Mono Analog Output Pin Mono Line Output Pin Beep Signal Input Pin IPGA (ALC1) Input Pin Microphone Analog Output Pin Microphone Input Pin (Mono Input) MIC Power Supply Pin for Microphone Common Voltage Output Pin. Common Voltage = 0.45 x AVDD Bias voltage of ADC inputs and DAC outputs. Note : All input pins except analog input pins (MIC, AIN, MIN, BEEP and VIN pins) should not be left floating. Note : The exposed pad on the bottom surface of the package must be open. MS0396-E-00 -4- 2005/06 ASAHI KASEI [AK4632] Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name Analog Input Analog Output Digital Input Digital Output MIC, AIN, BEEP, MIN, VSAG MICOUT, MPI, AOUT, MOUT, SPP, SPN, VOUT MCKI, SDTI, FCK(when M/S bit = "0"), BICK(when M/S bit = "0") MCKO, SDTO, FCK(when M/S bit = "1"), BICK(when M/S bit = "1") Setting These pins should be open and each path should be switched off. These pins should be open. These pins should be connected to DVSS. These pins should be open. ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS, SVSS=0V; Note 1) Parameter Symbol min Power Supplies: Analog AVDD -0.3 Digital DVDD -0.3 Speaker-Amp SVDD -0.3 Video VVDD -0.3 |AVSS - DVSS| (Note 2) GND1 |AVSS - SVSS| (Note 2) GND2 Input Current, Any Pin Except Supplies IIN Analog Input Voltage(Audio) (Note 3) VINA -0.3 Analog Input Voltage(Video) (Note 4) VINV -0.3 Digital Input Voltage VIND -0.3 Ambient Temperature (powered applied) Ta -10 Storage Temperature Tstg -65 Maximum Power Dissipation (Note 5) Pd - max 6.0 6.0 6.0 6.0 0.3 0.3 10 AVDD+0.3 VVDD+0.3 DVDD+0.3 70 150 700 Units V V V V V V mA V V V C C mW Note 1. All voltages with respect to ground. Note 2. AVSS, DVSS and SVSS must be connected to the same analog ground plane. Note 3. MIC, AIN, BEEP, MIN pins Note 4. VIN pin Note 5. In case that PCB wiring density is 100%. This power is the AK4632 internal dissipation that does not include power of externally connected speaker. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. MS0396-E-00 -5- 2005/06 ASAHI KASEI [AK4632] RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS, SVSS=0V; Note 1) Parameter Symbol min typ Power Supplies Analog AVDD 2.6 3.3 (Note 6) Digital DVDD 2.6 3.3 Speaker-Amp (Note 7) SVDD 2.6 3.3 / 5.0 Video (Note 8) VVDD 2.8 or AVDD 3.3 / 5.0 Difference AVDD-DVDD -0.3 0 max 3.6 3.6 5.25 5.25 0.3 Units V V V V V Note 1. All voltages with respect to ground Note 6. The power up sequence between AVDD, DVDD and SVDD is not critical. When the power supplies are partially powered OFF, the AK4632 must be reset by bringing PDN pin "L" after these power supplies are powered ON again. Note 7. SVDD = 2.6 3.6V when 8 dynamic speaker is connected to the AK4632. If SVDD is more than 3.6V when 8 dynamic speaker is connected to the AK4632, the output of Speaker-Amp should be restricted in consideration of maximum power dissipation as the following. SPoMax SPKMPD Rmin Vmax : Maximum Output Power of SPK-Amp[mW] : Maximum Power Dissipation of SPK-Amp[mW] : Minimum Impedance of speaker[] : Maximum permission output voltage of SPK-Amp[Vrms] SPKMPD = 700 - AVDD(max) x 17.5 - VVDD(max) x 12 - SVDD(max) x 27 A = 2 x sqrt(2) x SVDD(max) / B = A x A - 4 x Rmin x SPKMPD / 1000 Vmax= (A - sqrt(B)) / 2 SPoMax = 1000 x Vmax x Vmax / Rmin Maximum Output Power of SPK-Amp at B < 0 : No limitation Maximum Output Power of SPK-Amp at B 0: This power should be less than or equal to SPoMax[mW]. Regardless of the condition of B, the distortion of output signal increases, when SPK-Amp output power exceeds 240mW. Note 8. Minimum value is higher value between 2.8V and AVDD[V]. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0396-E-00 -6- 2005/06 ASAHI KASEI [AK4632] ANALOG CHRACTERISTICS (Ta=25C; AVDD, DVDD, SVDD, VVDD=3.3V; AVSS=DVSS=SVSS=0V; fs=8kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz 3.4kHz; EXT Slave Mode; unless otherwise specified) min typ max Units Parameter MIC Amplifier Input Resistance 20 30 40 k Gain (MGAIN1-0 bits = "00") dB 0 dB 20 (MGAIN1-0 bits = "01") dB 26 (MGAIN1-0 bits = "10") dB 32 (MGAIN1-0 bits = "11") MIC Power Supply: MPI pin Output Voltage (Note 9) 2.22 2.47 2.72 V Load Resistance 2 k Load Capacitance 30 pF Input PGA Characteristics: Input Resistance (Note 10) 5 10 15 k Step Size 0.05 0.5 0.9 dB Gain Control Range +27.5 dB -8 ADC Analog Input Characteristics: MIC IPGA ADC, MIC Gain=20dB, IPGA=0dB, ALC1=OFF Resolution 16 Bits Input Voltage (MIC Gain=20dB, Note 11) 0.168 0.198 0.228 Vpp 68 80 dB S/(N+D) (-1dBFS) (Note 12) 75 85 dB D-Range (-60dBFS) S/N 75 85 dB DAC Characteristics: Resolution 16 Bits Mono Line Output Characteristics: AOUT pin, DAC AOUT, RL=10k 1.78 1.98 2.18 Vpp Output Voltage (Note 13) 73 85 dB S/(N+D) (0dBFS) (Note 12) 83 93 dB D-Range (-60dBFS) 83 93 dB S/N 10 Load Resistance k 30 pF Load Capacitance Note 9. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ) Note 10. When IPGA Gain is changed, this typical value changes between 8k and 11k. Note 11. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ) Note 12. When a PLL reference clock is FCK pin in PLL Slave Mode, S/(N+D) is 77dB (typ). Note 13. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ) MS0396-E-00 -7- 2005/06 ASAHI KASEI [AK4632] min typ max Units Parameter Speaker-Amp Characteristics: SPP/SPN pins, MIN SPP/SPN, ALC2=OFF, RL=8, BTL, SVDD=3.3V Output Voltage 2.47 3.09 3.71 Vpp SPKG1-0 bits = "00" (-0.5dBFS) (Note 14) 3.10 4.00 4.80 Vpp SPKG1-0 bits = "01" (-0.5dBFS) S/(N+D) at 150mW Output 20 60 dB at 240mW Output 50 dB at 400mW Output 20 dB 80 90 dB S/N (Note 16) Load Resistance 8 30 pF Load Capacitance Speaker-Amp Characteristics: MIN SPP/SPN pins, ALC2=OFF, CL=3F, Rserial=10 x 2, BTL, SVDD=5.0V Output Voltage 6.72 Vpp SPKG1-0 bits = "10" (Note 14) 6.80 8.50 10.20 Vpp SPKG1-0 bits = "11" 60 dB S/(N+D) (Note 14) SPKG1-0 bits = "10" (Note 15) 20 50 dB SPKG1-0 bits = "11" 80 80 90 dB S/N (Note 15) (Note 16) Load Impedance (Note 17) 50 3 Load Capacitance F BEEP Input: BEEP pin, External Input Resistance= 20k Maximum Input Voltage (Note 18) 1.98 Vpp Output Voltage (Input Voltage=0.6Vpp) 0.74 1.48 2.22 Vpp BEEP SPP/SPN (SPKG1-0 bits = "00") 0.3 0.6 0.9 Vpp BEEP AOUT Mono Input: MIN pin 2.18 Vpp Maximum Input Voltage (Note 19) 12 24 36 Input Resistance (Note 20) k Mono Output: MOUT pin, DAC MOUT 1.78 1.98 2.18 Vpp Output Voltage (Note 21) Load Resistance 10 k 30 pF Load Capacitance Note 14. The full scale of Input signal of MIN pin is 1.98Vpp. Note 15. In case of measuring between SPP pin and SPN pin directly. Note 16. There are no relations with the setup of SPKG1-0 bits, and it is the same value. Note 17. Load impedance is total impedance of series resistance and piezo speaker impedance at 1kHz in Figure 35. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 10 or more series resistors should be connected at both SPP and SPN pins, respectively. Note 18. The maximum input voltage of the BEEP is proportional to AVDD voltage and external input resistance(Rin). Vout = 0.6 x AVDD x Rin/20k(max). Note 19. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.66 x AVDD (max) Note 20. When ALC2 Gain is changed, this typical value changes between 22k and 26k. Note 21. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ) MS0396-E-00 -8- 2005/06 ASAHI KASEI [AK4632] Parameter min Y Input Characteristics: Maximum Input Voltage (Note 22) Pull Down Current V Output Characteristics: Output Gain VIN=100kHz (GCA=0dB) 5.0 Maximum Output at DC output 2.4 Voltage at Sag Compensation Output 100F+2.2 uF, VVDD 3.135 V at Sag Compensation Output 47F+1.0uF, VVDD 3.135 V Clamp Voltage at DC output S/N BW=100kH 6MHz Secondary Distortion VIN=3.58MHz, 1.0Vpp(Sin Wave) (Note 23) Load Resistance 140 Load Capacitance C1(See Figure 2) C2(See Figure 2) (Note 24) LPF Frequency Response -3.0 Response at 6.75MHz Input=1.26Vpp, Sin Wave Response at 27MHz (0dB at 100kHz) Group Delay |GD3MHz -GD6MHz| GCA Characteristics: Step Size 0.1 GCA = -1.0dB +10.5dB Power Supplies Power Up (PDN = "H") All Circuit Power-up: (Note 25) AVDD+DVDD fs=8kHz 9 fs=48kHz 11.5 SVDD: Speaker-Amp Normal Operation (SPPS bit = "1", No Output) SVDD=3.3V 7 SVDD=5.0V 9 VVDD (Note 26) VVDD=3.3V 7.5 VVDD=5.0V 8 Power Down (PDN = "L") (Note 27) 10 AVDD+DVDD+SVDD+VVDD typ 1.2 2.0 6.0 2.52 2.4 2.4 0.15 66 -45 150 -0.5 -30 10 0.5 max 7.0 15 400 -20 100 0.9 Units Vpp A dB Vpp Vpp Vpp V dB dB pF pF dB dB nsec dB 17.5 27 12 100 mA mA mA mA mA mA A Note 22. Input Voltage doesn't depend on VVDD. Note 23. In the case of using Sag Compensation Circuit with 47F+ 1.0uF and SAGC1-0 bits = "10" Note 24. R1 and C2 compose of Low Pass Filter(LPF) in Figure 2. The cut off frequency of LPF is 10.6MHz at C2 = 400pF. R1 75 ohm Video Signal Output C1 C2 R2 75 ohm Figure 2. Load Capacitance C1 and C2 MS0396-E-00 -9- 2005/06 ASAHI KASEI [AK4632] Note 25. PLL Master Mode (MCKI=12.288MHz) and PMV=PMMIC = PMADC = PMDAC = PMSPK = PMVCM = PMPLL = MCKO = PMAO = PMBP = MPWR = M/S ="1". And output current from MPI pin is 0mA. When the AK4632 is EXT mode (PMPLL = MCKO = M/S = "0"), "AVDD+DVDD" is typically 7mA@fs=8kHz, 9.5mA@fs=48kHz). Note 26. This is the case of SAGC bits = "00" and no load resistance and capacitance. When SAGC bits = "10" and Black signal is output, this current is typ.8mA. In the case of DC Output, this current increases by DC voltage / 150 . DC Output Voltage is 0V at PMV bit = "0", and then DC current doesn't flow. When any signal isn't input at using Sag Compensation Circuit, PMV bit should be set to "0". Note 27. MCKI pin is fixed to DVSS and all digital inputs pins except MCKI pin are fixed to DVSS or DVSS. FILTER CHRACTERISTICS (Ta = 25C; AVDD, DVDD = 2.6 3.6V; SVDD =2.6 5.25V; VVDD =2.8 5.25V; fs=8kHz) Parameter Symbol min typ max ADC Digital Filter (Decimation LPF): 0.16dB PB 0 3.0 Passband (Note 28) -0.66dB 3.5 -1.1dB 3.6 -6.9dB 4.0 Stopband (Note 28) SB 4.7 Passband Ripple PR 0.1 Stopband Attenuation SA 73 Group Delay (Note 29) GD 17.1 Group Delay Distortion GD 0 ADC Digital Filter (HPF): Frequency Response (Note 28) -3.0dB FR 0.62 -0.5dB 1.81 -0.1dB 3.99 DAC Digital Filter: Passband (Note 28) 0.1dB PB 0 3.6 -0.7dB 3.6 -6.0dB 4.0 Stopband (Note 28) SB 4.6 Passband Ripple PR 0.01 Stopband Attenuation SA 59 Group Delay (Note 29) GD 16.8 DAC Digital Filter + Analog Filter: Frequency Response: 0 3.4kHz FR 1.0 Units kHz kHz kHz kHz kHz dB dB 1/fs s Hz Hz Hz kHz kHz kHz dB dB 1/fs dB Note 28. The passband and stopband frequencies are proportional to fs (system sampling rate). For example, ADC is PB=0.45*fs (@-1.1dB). A reference of frequency response is 1kHz. Note 29. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 16-bit data of a channel from the input register to the output register of the ADC. This time includes the group delay of the HPF. For the DAC, this time is from setting the 16-bit data of a channel from the input register to the output of analog signal. DC CHRACTERISTICS (Ta = 25C; AVDD, DVDD = 2.6 3.6V; SVDD =2.6 5.25V) Parameter Symbol min High-Level Input Voltage VIH 70%DVDD Low-Level Input Voltage VIL High-Level Output Voltage (Iout=-80A) VOH DVDD-0.4 Low-Level Output Voltage (Iout= 80A) VOL Input Leakage Current Iin - typ - max 30%DVDD 0.4 10 Units V V V V A MS0396-E-00 - 10 - 2005/06 ASAHI KASEI [AK4632] SWITING CHARACTERISTICS (Ta = 25C; AVDD, DVDD = 2.6 3.6V; SVDD =2.6 5.25V ; VVDD =2.8 5.25V; CL=20pF) Parameter Symbol min typ max PLL Master Mode (PLL Reference Clock = MCKI pin) (Figure 3) MCKI Input: Frequency Pulse Width Low Pulse Width High MCKO Output: Frequency Duty Cycle except fs=29.4kHz, 32kHz fs=29.4kHz, 32kHz (Note 30) FCK Output: Frequency Duty Cycle BICK: Period (BCKO1-0 = "00") (BCKO1-0 = "01") (BCKO1-0 = "10") Duty Cycle Audio Interface Timing DSP Mode: (Figure 4, Figure 5) FCK "" to BICK "" (Note 31) FCK "" to BICK "" (Note 32) BICK "" to SDTO (BCKP = "0") BICK "" to SDTO (BCKP = "1") SDTI Hold Time SDTI Setup Time Except DSP Mode: (Figure 6) BICK "" to FCK Edge FCK to SDTO (MSB) (Except I2S mode) BICK "" to SDTO SDTI Hold Time SDTI Setup Time fCLK tCLKL tCLKH fMCK dMCK dMCK fFCK dFCK tBCK tBCK tBCK dBCK 11.2896 0.4/fCLK 0.4/fCLK 40 8 256 x fFCK 50 33 50 1/16fFCK 1/32fFCK 1/64fFCK 50 27.0 60 48 - Units MHz ns ns kHz % % kHz % ns ns ns % tDBF tDBF tBSD tBSD tSDH tSDS tBFCK tFSD tBSD tSDH tSDS 0.5 x tBCK -40 0.5 x tBCK -40 -70 -70 50 50 -40 -70 -70 50 50 0.5 x tBCK 0.5 x tBCK - 0.5 x tBCK + 40 0.5 x tBCK +40 70 70 40 70 70 - ns ns ns ns ns ns ns ns ns ns ns MS0396-E-00 - 11 - 2005/06 ASAHI KASEI [AK4632] Parameter Symbol min PLL Slave Mode (PLL Reference Clock: FCK pin) (Figure 7, Figure 8) FCK: Frequency DSP Mode: Pulse Width High Except DSP Mode: Duty Cycle BICK: Period Pulse Width Low Pulse Width High FCK: Frequency DSP Mode: Pulse width High Except DSP Mode: Duty Cycle BICK: Period (PLL3-0 = "0001") (PLL3-0 = "0010") (PLL3-0 = "0011") Pulse Width Low Pulse Width High MCKI Input: Frequency Pulse Width Low Pulse Width High MCKO Output: Frequency Duty Cycle except fs=29.4kHz, 32kHz fs=29.4kHz, 32kHz (Note 30) FCK: Frequency DSP Mode: Pulse width High Except DSP Mode: Duty Cycle BICK: Period Pulse Width Low Pulse Width High Audio Interface Timing DSP Mode: (Figure 10,Figure 11) FCK "" to BICK "" (Note 31) FCK "" to BICK "" (Note 32) BICK "" to FCK "" (Note 31) BICK "" to FCK "" (Note 32) BICK "" to SDTO (BCKP = "0") BICK "" to SDTO (BCKP = "1") SDTI Hold Time SDTI Setup Time Except DSP Mode: (Figure 13) FCK Edge to BICK "" (Note 33) BICK "" to FCK Edge (Note 33) FCK to SDTO (MSB) (Except I2S mode) BICK "" to SDTO SDTI Hold Time SDTI Setup Time fFCK tFCKH duty tBCK tBCKL tBCKH fFCK tFCKH duty tBCK tBCK tBCK tBCKL tBCKH fCLK fCLKL fCLKH fMCK dMCK dMCK fFCK tFCKH duty tBCK tBCKL tBCKH 7.35 tBCK-60 45 1/64fFCK 240 240 7.35 tBCK-60 45 0.4 x tBCK 0.4 x tBCK 11.2896 0.4/fCLK 0.4/fCLK 40 8 tBCK-60 45 1/64fFCK 0.4 x tBCK 0.4 x tBCK typ 8 8 1/16fFCK 1/32fFCK 1/64fFCK 256 x fFCK 50 33 - max 26 1/fFCK-tBFCK 55 1/16fFCK 48 1/fFCK-tBFCK 55 27.0 60 48 1/fFCK-tBFCK 55 1/16fFCK - Units kHz ns % ns ns ns kHz ns % ns ns ns ns ns MHz ns ns kHz % % kHz ns % ns ns ns PLL Slave Mode (PLL Reference Clock: BICK pin) (Figure 7, Figure 8) PLL Slave Mode (PLL Reference Clock: MCKI pin) (Figure 9) tFCKB tFCKB tBFCK tBFCK tBSD tBSD tSDH tSDS tFCKB tBFCK tFSD tBSD tSDH tSDS 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK 50 50 50 50 50 50 - 80 80 80 80 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns MS0396-E-00 - 12 - 2005/06 ASAHI KASEI [AK4632] Parameter EXT Slave Mode (Figure 12) MCKI Frequency: 256fs 512fs 1024fs Pulse Width Low Pulse Width High FCK Frequency (MCKI = 256fs) (MCKI = 512fs) (MCKI = 1024fs) Duty Cycle BICK Period BICK Pulse Width Low Pulse Width High Audio Interface Timing (Figure 13) FCK Edge to BICK "" (Note 33) BICK "" to FCK Edge (Note 33) FCK to SDTO (MSB) (Except I2S mode) BICK "" to SDTO SDTI Hold Time SDTI Setup Time Symbol fCLK fCLK fCLK tCLKL tCLKH fFCK fFCK fFCK duty tBCK tBCKL tBCKH tFCKB tBFCK tFSD tBSD tSDH tSDS min 1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK 7.35 7.35 7.35 45 312.5 130 130 50 50 50 50 typ 2.048 4.096 8.192 8 8 8 - Max 12.288 13.312 13.312 48 26 13 55 80 80 - Units MHz MHz MHz ns ns kHz kHz % ns ns ns ns ns ns ns ns ns Note 30. Duty Cycle = (the width of "L" ) / (the period of clock) x 100 Note 31. MSBS, BCKP bits = "00" or "11" Note 32. MSBS, BCKP bits = "01" or "10" Note 33. BICK rising edge must not occur at the same time as FCK edge. Parameter Control Interface Timing: CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "H" Time CSN "" to CCLK "" CCLK "" to CSN "" Reset Timing PDN Pulse Width PMADC "" to SDTO valid (Note 34) (Note 35) Symbol tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tPD tPDV min 200 80 80 40 40 150 150 50 150 - typ 1059 max - Units ns ns ns ns ns ns ns ns ns 1/fs Note 34. The AK4632 can be reset by the PDN pin = "L" Note 35. This is the count of FCK "" from the PMADC = "1". MS0396-E-00 - 13 - 2005/06 ASAHI KASEI [AK4632] Timing Diagram 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fFCK FCK dFCK 1/fMCK dFCK 50%DVDD MCKO tMCKOH tMCKOL 50%DVDD dMCK = tMCKOL x fMCK x 100 Figure 3. Clock Timing (PLL Master mode) FCK tDBF tBCK dBCK BICK (BCKP = "0") 50%DVDD 50%DVDD BICK (BCKP = "1") tBSD SDTO 50%DVDD MSB 50%DVDD tSDS tSDH VIH MSB VIL SDTI Figure 4. Audio Interface Timing (PLL Master mode & DSP mode: MSBS = "0") MS0396-E-00 - 14 - 2005/06 ASAHI KASEI [AK4632] FCK tDBF tBCK dBCK BICK (BCKP = "1") 50%DVDD 50%DVDD BICK (BCKP = "0") tBSD SDTO 50%DVDD MSB 50%DVDD tSDS tSDH VIH VIL SDTI MSB Figure 5. Audio Interface Timing (PLL Master mode & DSP mode: MSBS = "1") FCK 50%DVDD tBFCK dBCK 50%DVDD BICK tFSD tBSD SDTO tSDS tSDH 50%DVDD VIH SDTI VIL Figure 6. Audio Interface Timing (PLL Master mode & Except DSP mode) MS0396-E-00 - 15 - 2005/06 ASAHI KASEI [AK4632] 1/fFCK VIH VIL tFCKH tBCK VIH BICK (BCKP = "0") tBCKH tBCKL VIH BICK (BCKP = "1") VIL VIL tBFCK FCK Figure 7. Clock Timing (PLL Slave mode; PLL Reference clock = FCK or BICK pin & DSP mode; MSBS = 0) 1/fFCK VIH VIL tFCKH tBCK VIH BICK (BCKP = "1") tBCKH tBCKL VIH BICK (BCKP = "0") VIL VIL tBFCK FCK Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = FCK or BICK pin & DSP mode; MSBS = 1) MS0396-E-00 - 16 - 2005/06 ASAHI KASEI [AK4632] 1/fCLK VIH MCKI VIL tCLKH 1/fFCK VIH FCK VIL tFCKH tBCK VIH BICK VIL tBCKH 1/fMCK tBCKL tFCKL tCLKL MCKO tMCKOH tMCKOL 50%DVDD dMCK = tMCKOL x fMCK x 100 Figure 9. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode) MS0396-E-00 - 17 - 2005/06 ASAHI KASEI [AK4632] tFCKH VIH FCK tFCKB VIL VIH BICK (BCKP = "0") VIH BICK (BCKP = "1") tBSD VIL VIL SDTO MSB tSDH 50%DVDD tSDS VIH SDTI MSB VIL Figure 10. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = 0) tFCKH VIH FCK tFCKB VIL VIH BICK (BCKP = "1") VIH BICK (BCKP = "0") tBSD VIL VIL SDTO MSB 50%DVDD tSDS tSDH VIH SDTI MSB VIL Figure 11. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = 1) MS0396-E-00 - 18 2005/06 ASAHI KASEI [AK4632] 1/fCLK VIH MCKI tCLKH 1/fFCK VIH FCK tFCKH tBCK VIH VIL tBCKH tBCKL tFCKL VIL tCLKL VIL BICK Figure 12. Clock Timing (EXT Slave mode) VIH FCK VIL tBFCK tFCKB VIH BICK VIL tFSD tBSD SDTO tSDS MSB tSDH 50%DVDD VIH SDTI VIL Figure 13. Audio Interface Timing (PLL, EXT Slave mode & Except DSP mode) MS0396-E-00 - 19 - 2005/06 ASAHI KASEI [AK4632] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 C0 tCCK tCDH VIH R/W VIL Figure 14. WRITE Command Input Timing tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI D2 D1 D0 VIL Figure 15. WRITE Data Input Timing VIH CSN VIL tPDV SDTO 50%DVDD Figure 16. Power Down & Reset Timing 1 tPD PDN VIL Figure 17. Power Down & Reset Timing 2 MS0396-E-00 - 20 - 2005/06 ASAHI KASEI [AK4632] OPERATION OVERVIEW System Clock There are the following four clock modes to interface with external devices. (See Table 1 and Table 2) Mode PMPLL bit M/S bit PLL3-0 bit PLL Master Mode 1 1 See Table 4 PLL Slave Mode 1 1 0 See Table 4 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 1 0 See Table 4 (PLL Reference Clock: FCK or BICK pin) EXT Slave Mode 0 0 X Invalid state (Note 36) 0 1 X Table 1. Clock Mode Setting (X: Don't care) MCKPD bit 0 0 1 0 X Figure Figure 19 Figure 20 Figure 21 Figure 22 - Note 36. If this mode is selected, the invalid clocks are output from MCKO, FCK and BICK pins. Mode PLL Master Mode MCKO bit 0 1 PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 (PLL Reference Clock: FCK or BICK pin) EXT Slave Mode 0 1 0 MCKO pin "L" Output 256fs Output "L" Output 256fs Output "L" Output MCKI pin Master Clock Input for PLL (Note 37) Master Clock Input for PLL (Note 37) GND BICK pin 16fs/32fs/64fs Output 16fs/32fs/64fs Input 16fs/32fs/64fs Input FCK pin 1fs Output 1fs Input 1fs Input 1fs Input 256fs/ 512fs/ 32fs 0 "L" Output 1024fs Input Input Note 37. 11.2896MHz/12MHz/12.288MHz/13.5MHz/24MHz/27MHz Table 2. Clock pins state in Clock Mode [Pull-down resistor of MCKI pin] When the master clock is input, MCKPD bit should be "0". When the MCKI pin is floating, the pin should be pulled-down by internal 25k resistor at MCKPD bit = "1"(Default). MCKI MCKPD bit ="0" 25k AK4632 Figure 18. Pull-down resistor of MCKI pin MS0396-E-00 - 21 - 2005/06 ASAHI KASEI [AK4632] Master Mode/Slave Mode The M/S bit selects either master or slave modes. M/S bit = "1" selects master mode and "0" selects slave mode. When the AK4632 is power-down mode (PDN pin = "L") and exits reset state, the AK4632 is slave mode. After exiting reset state, the AK4632 goes master mode by changing M/S bit = "1". When the AK4632 is used by master mode, FCK and BICK pins are a floating state until M/S bit becomes "1". FCK and BICK pins of the AK4632 should be pulled-down or pulled-up by about 100k resistor externally to avoid the floating state. M/S bit Mode 0 Slave Mode Default 1 Master Mode Table 3. Select Master/Salve Mode PLL Mode When PMPLL bit is "1", a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK4632 is supplied to a stable clocks after PLL is powered-up (PMPLL bit = "0" "1") or sampling frequency changes. 1) Setting of PLL Mode Mode PLL3 bit 0 0 0 0 0 0 0 0 1 1 PLL2 bit 0 0 0 0 1 1 1 1 1 1 Others PLL1 bit 0 0 1 1 0 0 1 1 0 0 0 1 2 3 4 5 6 7 12 13 Others R and C of PLL Input VCOC pin Reference Frequency Clock Input C[F] R[] Pin 0 FCK pin 1fs 6.8k 220n 1 BICK pin 16fs 10k 4.7n 0 BICK pin 32fs 10k 4.7n 1 BICK pin 64fs 10k 4.7n 0 MCKI pin 11.2896MHz 10k 4.7n 1 MCKI pin 12.288MHz 10k 4.7n 0 MCKI pin 12MHz 10k 4.7n 1 MCKI pin 24MHz 10k 4.7n 0 MCKI pin 13.5MHz 10k 10n 1 MCKI pin 27MHz 10k 10n N/A Table 4. Setting of PLL Mode (*fs: Sampling Frequency) PLL0 bit PLL Lock Time (max) 160ms 2ms 2ms 2ms 40ms 40ms 40ms 40ms 40ms 40ms Default 2) Setting of sampling frequency in PLL Mode. When PLL2 bit is "1" (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS2-0 bits as defined in Table 5. Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency 0 0 0 0 0 8kHz Default 1 0 0 0 1 12kHz 2 0 0 1 0 16kHz 3 0 0 1 1 24kHz 4 0 1 0 0 7.35kHz 5 0 1 0 1 11.025kHz 6 0 1 1 0 14.7kHz 7 0 1 1 1 22.05kHz 10 1 0 1 0 32kHz 11 1 0 1 1 48kHz 14 1 1 1 0 29.4kHz 15 1 1 1 1 44.1kHz Others Others N/A Table 5. Setting of Sampling Frequency at PLL2 bit = "1" and PMPLL bit = "1" MS0396-E-00 - 22 2005/06 ASAHI KASEI [AK4632] When PLL2 bit is "0" (PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS3, FS1-0 bits. (See Table 6) Mode 0 1 2 3 6 7 Others FS2 bit FS1 bit FS0 bit Sampling Frequency Range Don't care 0 Default 0 7.35kHz fs 8kHz Don't care 1 0 8kHz < fs 12kHz Don't care 0 1 12kHz < fs 16kHz Don't care 1 1 16kHz < fs 24kHz Don't care 0 1 24kHz < fs 32kHz Don't care 1 1 32kHz < fs 48kHz Others N/A Table 6. Setting of Sampling Frequency at PLL2 bit = "0" and PMPLL bit = "1" FS3 bit 0 0 0 0 1 1 PLL Unlock State 1) PLL Master Mode (PMPLL bit = "1", M/S bit = "1") In this mode, irregular frequency clocks are output from FCK, BICK and MCKO pins after PMPLL bit = "0" "1" or sampling frequency is changed. After that PLL is unlocked, BICK and FCK pins output "L" for a moment, and invalid frequency clock is output from MCKO pin at MCKO bit = "1". If MCKO bit is "0", MCKO pin is output to "L". (See Table 7) After the PLL is locked, a first period of FCK and BICK may be invalid clock, but these clocks return to normal state after a period of 1/fs. MCKO pin BICK pin FCK pin MCKO bit = "0" MCKO bit = "1" Invalid Invalid Invalid After that PMPLL bit "0" "1" "L" Output PLL Unlock Invalid "L" Output "L" Output "L" Output 256fs Output 1fs Output PLL Lock See Table 9 "L" Output Table 7. Clock Operation at PLL Master Mode (PMPLL bit = "1", M/S bit = "1") PLL State 2) PLL Slave Mode (PMPLL bit = "1", M/S bit = "0") In this mode, an invalid clock is output from MCKO pin after PMPLL bit = "0" "1" or sampling frequency is changed. After that, 256fs is output from MCKO pin when PLL is locked. ADC and DAC output invalid data when the PLL is unlocked. For DAC, the output signal should be muted by writing "0" to DACA and DACM bits in Addr=02H. MCKO pin MCKO bit = "0" MCKO bit = "1" Invalid After that PMPLL bit "0" "1" "L" Output PLL Unlock Invalid "L" Output PLL Lock 256fs Output "L" Output Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = "1", M/S bit = "0") PLL State MS0396-E-00 - 23 - 2005/06 ASAHI KASEI [AK4632] PLL Master Mode (PMPLL bit = "1", M/S bit = "1") When an external clock (11.2896MHz, 12MHz , 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to MCKI pin, the MCKO, BICK and FCK clocks are generated by an internal PLL circuit. The MCKO output frequency is fixed to 256fs, the output is enabled by MCKO bit. The BICK is selected among 16fs, 32fs or 64fs, by BCKO1-0 bits. (See Table 9) When BICK output frequency is 16fs, the audio interface format supports only Mode 0 (DSP Mode). 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz AK4632 MCKI MCKO BICK FCK SDTO SDTI 256fs 16fs, 32fs, 64fs 1fs DSP or P MCLK BCLK FCK SDTI SDTO Figure 19. PLL Master Mode Mode 0 1 2 3 BICK Output Frequency 0 0 16fs 0 1 32fs 1 0 64fs 1 1 N/A Table 9. BICK Output Frequency at Master Mode BCKO1 BCKO0 Default MS0396-E-00 - 24 - 2005/06 ASAHI KASEI [AK4632] PLL Slave Mode (PMPLL bit = "1", M/S bit = "0") A reference clock of PLL is selected among the input clocks to MCKI, BICK or FCK pin. The required clock to the AK4632 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits. When BICK input frequency is 16fs, the audio interface format supports only Mode 0 (DSP Mode). a) PLL reference clock: BICK or FCK pin In the case of using BICK as PLL reference clock, the sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits. In the case of using FCK, the sampling frequency corresponds to 7.35kHz to 26kHz. (SeeTable 6) AK4632 MCKO MCKI BICK FCK SDTO SDTI 16fs, 32fs, 64fs 1fs BCLK FCK SDTI SDTO DSP or P Figure 20. PLL Slave Mode 1 (PLL Reference Clock: FCK or BICK pin) b) PLL reference clock: MCKI pin BICK and FCK inputs should be synchronized with MCKO output. The phase between MCKO and FCK dose not matter. Sampling frequency can be selected by FS3-0 bits. (See Table 5) 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz AK4632 MCKI MCKO BICK FCK SDTO SDTI 256fs 16fs, 32fs, 64fs 1fs DSP or P MCLK BCLK FCK SDTI SDTO Figure 21. PLL Slave Mode 2 (PLL Reference Clock: MCKI pin) The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC is in operation (PMADC bit = "1" or PMDAC bit = "1"). If these clocks are not provided, the AK4632 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADC bit =PMDAC bit = "0"). MS0396-E-00 - 25 - 2005/06 ASAHI KASEI [AK4632] EXT Slave Mode (PMPLL bit = "0", M/S bit = "0") When PMPLL bit is "0", the AK4632 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 512fs or 1024fs), FCK (fs) and BICK (32fs). The master clock (MCKI) should be synchronized with FCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS3-0 bits. (See Table 10) Mode 0 1 2 3 MCKI Input Sampling Frequency Frequency Range Don't care 0 256fs 0 7.35kHz fs 48kHz Don't care 1 1024fs 0 7.35kHz < fs 13kHz Don't care 0 256fs 1 7.35kHz < fs 48kHz Don't care 1 512fs 1 7.35kHz < fs 26kHz Table 10. MCKI Frequency at EXT Slave Mode (PMPLL bit = "0", M/S bit = "0") FS3-2 bits FS1 bit FS0 bit Default External Slave Mode does not support Mode 0 (DSP Mode) of Audio Interface Format. The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. When the out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output through AOUT amp at fs=8kHz is shown in Table 11. S/N (fs=8kHz, 20kHzLPF + A-weight) 256fs 83dB 512fs 93dB 1024fs 93dB Table 11. Relationship between MCKI and S/N of AOUT MCKI The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC is in operation (PMADC bit = "1" or PMDAC bit = "1"). If these clocks are not provided, the AK4632 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADC bit = PMDAC bit = "0"). AK4632 MCKO 256fs, 512fs or 1024fs MCKI BICK FCK SDTO SDTI 32fs, 64fs 1fs MCLK BCLK FCK SDTI SDTO DSP or P Figure 22. EXT Slave Mode MS0396-E-00 - 26 - 2005/06 ASAHI KASEI [AK4632] Audio Interface Format Four types of data formats are available and are selected by setting the DIF1-0 bits. (See Table 12) In all modes, the serial data is MSB first, 2's complement format. Audio interface formats can be used in both master and slave modes. FCK and BICK are output from AK4632 in master mode, but must be input to AK4632 in slave mode. In Mode 1-3, the SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising edge. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 0 1 0 1 SDTO (ADC) SDTI (DAC) BICK DSP Mode DSP Mode 16fs MSB justified MSB justified 32fs MSB justified MSB justified 32fs I2S compatible I2S compatible 32fs Table 12. Audio Interface Format Figure See Table 13 Figure 27 Figure 28 Figure 29 Default In Mode0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits. When BCKP bit is "0", SDTO data is output by rising edge of BICK, SDTI data is latched by falling edge of BICK. When BCKP bit is "1", SDTO data is output by falling edge of BICK, SDTI data is latched by rising edge of BICK. MSB data position of SDTO and SDTI can be shifted by MSBS bit. The shifted period is a half of BICK. MSBS bit BCKP bit Audio Interface Format 0 0 Figure 23 0 1 Figure 24 1 0 Figure 25 1 1 Figure 26 Table 13. Audio Interface Format in Mode 0 Default If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, "-1" at 16bit data is converted to "-1" at 8-bit data. And when the DAC playbacks this 8-bit data, "-1" at 8-bit data will be converted to "-256" at 16-bit data and this is a large offset. This offset can be removed by adding the offset of "128" to 16-bit data before converting to 8-bit data. System Reset Upon power-up, reset the AK4632 by bringing the PDN pin = "L". This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle that starts when the PMADC bit is changed from "0" to "1". The initialization cycle time is 1059/fs, or 133ms@fs=8kHz. During the initialization cycle, the ADC digital data outputs of both channels are forced to a 2's compliment, "0". The ADC output reflects the analog input signal after the initialization cycle is complete. The DAC does not require an initialization cycle. MS0396-E-00 - 27 - 2005/06 ASAHI KASEI [AK4632] FCK 15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0 BICK(16fs) SDTO(o) SDTI(i) 15 0 0 15 14 15 14 8 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 15 14 15 14 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 15 15 0 1 2 8 14 15 16 17 18 29 30 31 0 1 2 8 8 9 10 11 12 13 30 31 0 BICK(32fs) SDTO(o) SDTI(i) 15 14 15 14 8 2 1 0 15 14 15 14 8 2 1 0 2 1 0 Don't Care 8 2 1 0 Don't Care 1/fs 15:MSB, 0:LSB 1/fs Figure 23. Mode 0 Timing (BCKP = "0", MSBS = "0") FCK 15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0 BICK(16fs) SDTO(o) SDTI(i) 15 0 0 15 14 15 14 8 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 15 14 15 14 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 15 15 0 1 2 8 14 15 16 17 18 29 30 31 0 1 2 8 8 9 10 11 12 13 30 31 0 BICK(32fs) SDTO(o) SDTI(i) 15 14 15 14 8 2 1 0 15 14 15 14 8 2 1 0 2 1 0 Don't Care 8 2 1 0 Don't Care 1/fs 15:MSB, 0:LSB 1/fs Figure 24. Mode 0 Timing (BCKP = "1", MSBS = "0") MS0396-E-00 - 28 - 2005/06 ASAHI KASEI [AK4632] FCK 15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0 BICK(16fs) SDTO(o) SDTI(i) 15 0 0 15 14 15 14 8 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 15 14 15 14 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 15 15 0 1 2 8 14 15 16 17 18 29 30 31 0 1 2 8 8 9 10 11 12 13 30 31 0 BICK(32fs) SDTO(o) SDTI(i) 15 14 15 14 8 2 1 0 15 14 15 14 8 2 1 0 2 1 0 Don't Care 8 2 1 0 Don't Care 1/fs 15:MSB, 0:LSB 1/fs Figure 25. Mode 0 Timing (BCKP = "0", MSBS = "1") FCK 15 0 1 2 8 8 9 10 11 12 13 14 15 0 1 2 8 8 9 10 11 12 13 14 15 0 BICK(16fs) SDTO(o) SDTI(i) 15 0 0 15 14 15 14 8 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 15 14 15 14 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 15 15 0 1 2 8 14 15 16 17 18 29 30 31 0 1 2 8 8 9 10 11 12 13 30 31 0 BICK(32fs) SDTO(o) SDTI(i) 15 14 15 14 8 2 1 0 15 14 15 14 8 2 1 0 2 1 0 Don't Care 8 2 1 0 Don't Care 1/fs 15:MSB, 0:LSB 1/fs Figure 26. Mode 0 Timing (BCKP = "1", MSBS = "1") MS0396-E-00 - 29 - 2005/06 ASAHI KASEI [AK4632] FCK 0 1 2 3 8 9 10 11 12 13 14 15 0 1 2 3 8 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) SDTI(i) 0 15 14 13 15 14 13 1 2 3 8 7 7 14 6 6 15 5 5 16 4 4 17 3 3 18 2 2 1 1 31 0 0 0 1 2 3 14 15 15 18 31 0 1 Don't Care 15 16 17 BICK(64fs) SDTO(o) SDTI(i) 15 14 13 2 1 0 15 Don't Care 15:MSB, 0:LSB Data 15 14 1 0 Don't Care 1/fs Figure 27. Mode 1 Timing FCK 0 1 2 8 9 10 11 12 13 14 15 0 1 2 8 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) SDTI(I) 0 15 14 8 7 6 5 4 3 2 1 0 15 15 14 1 2 3 8 7 14 6 15 5 16 4 17 3 18 2 1 31 0 0 1 2 3 14 Don't Care 14 15 16 17 18 31 0 15 1 BICK(64fs) SDTO(o) SDTI(i) 15 14 13 13 2 1 0 15 15 14 13 13 2 1 0 Don't Care Don't Care 15 15:MSB, 0:LSB Data 1/fs Figure 28. Mode 2 Timing MS0396-E-00 - 30 - 2005/06 ASAHI KASEI [AK4632] FCK 0 1 2 3 4 9 10 11 12 13 14 15 0 1 2 3 4 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) SDTI(i) 0 1 15 14 13 15 14 13 2 3 4 7 7 7 14 15 6 6 16 5 5 17 4 4 18 3 3 2 2 31 1 1 0 0 0 1 2 3 4 14 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) SDTI(i) 15 14 13 15 14 13 2 1 0 2 1 0 Don't Care Don't Care 15:MSB, 0:LSB Data 1/fs Figure 29. Mode 3 Timing Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.25Hz (@fs=8kHz) and scales with sampling rate (fs). MIC Gain Amplifier The AK4632 has a Gain Amplifier for Microphone input. This gain is 0dB, +20dB, +26dB or +32dB, selected by the MGAIN1-0 bit. The typical input impedance is 30k. MGAIN1 bit 0 0 1 1 MGAIN0 bit Input Gain 0 0dB 1 +20dB 0 +26dB 1 +32dB Table 14. Input Gain Default MIC Power The MPI pin supplies power for the Microphone. This output voltage is typically 0.75 x AVDD and the load resistance is minimum 2k. No capacitor must not be connected directly to MPI pin. (See Figure 30) MIC Power MPI pin 2k Microphone MIC pin MIC-Amp Figure 30. MIC Block Circuit MS0396-E-00 - 31 - 2005/06 ASAHI KASEI [AK4632] Manual Mode The AK4632 becomes a manual mode at ALC1 bit = "0". This mode is used in the case shown below. 1. After exiting reset state, set up the registers for the ALC1 operation (ZTM1-0, LMTH and etc) 2. When the registers for the ALC1 operation (Limiter period, Recovery period and etc) are changed. For example; When the change of the sampling frequency. 3. When IPGA is used as a manual volume. When IPGA6-0 bits are written at manual mode, the counter for zero cross time out is reset and restart. The IPGA6-0 bits value are reflected to IPGA at zero cross or zero cross time out. The time of zero cross time out is set by ZTM1-0 bits. When writing to IPGA6-0 bits continually, the control register should be written by an interval of more than zero crossing timeout. MIC-ALC Operation The ALC (Automatic Level Control) of MIC input is done by ALC1 block when ALC1 bit is "1". [1] ALC1 Limiter Operation When the ALC1 limiter is enabled, and IPGA output exceeds the ALC1 limiter detection level (LMTH), the IPGA value is attenuated by the amount defined in the ALC1 limiter ATT step (LMAT1-0 bits) automatically. When the ZELM bit = "1", the timeout period is set by the LTM1-0 bits. The operation for attenuation is done continuously until the input signal level becomes LMTH or less. If the ALC1 bit does not change into "0" after completing the attenuation, the attenuation operation repeats while the input signal level equals or exceeds LMTH. When the ZELM bit = "0", the timeout period is set by the ZTM1-0 bits. This enables the zero-crossing attenuation function so that the IPGA value is attenuated at the zero-detect points of the waveform. [2] ALC1 Recovery Operation The ALC1 recovery refers to the amount of time that the AK4632 will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the wait period used after completing an ALC1 limiter operation. If the input signal does not exceed the "ALC1 Recovery Waiting Counter Reset Level", the ALC1 recovery operation starts. The IPGA value increases automatically during this operation up to the reference level (REF6-0 bits). The ALC1 recovery operation is done at a period set by the WTM1-0 bits. Zero crossing is detected during WTM1-0 period, the ALC1 recovery operation waits WTM1-0 period and the next recovery operation starts. During the ALC1 recovery operation, when input signal level exceeds the ALC1 limiter detection level (LMTH), the ALC1 recovery operation changes immediately into an ALC1 limiter operation. In the case of "(Recovery waiting counter reset level) IPGA Output Level < Limiter detection level" during the ALC1 recovery operation, the wait timer for the ALC1 recovery operation is reset. Therefore, in the case of "(Recovery waiting counter reset level) > IPGA Output Level", the wait timer for the ALC1 recovery operation starts. The ALC1 operation corresponds to the impulse noise. When the impulse noise is input, the ALC1 recovery operation becomes faster than a normal recovery operation. MS0396-E-00 - 32 - 2005/06 ASAHI KASEI [AK4632] [3] Example of ALC1 Operation Table 15 shows the example of the ALC1 setting. In case of this example, ALC1 operation starts from 0dB. Register Name LMTH LTM1-0 ZELM ZTM1-0 WTM1-0 REF6-0 IPGA6-0 LMAT1-0 RATT ALC1 Comment fs=8kHz Operation -4dBFS Don't use Enable 16ms fs=16kHz Data Operation 1 -4dBFS 00 Don't use 0 Enable 01 16ms 01 47H 10H 00 0 1 16ms +27.5dB 0dB 1 step 1 step Enable Limiter detection Level Limiter operation period at ZELM = 1 Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM1-0 bits should be the same data 00 16ms as ZTM1-0 bits Maximum gain at recovery operation 47H +27.5dB IPGA gain at the start of ALC1 operation 10H 0dB Limiter ATT Step 00 1 step Recovery GAIN Step 0 1 step ALC1 Enable bit 1 Enable Table 15. Examples of the ALC1 Setting Data 1 00 0 00 The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1 operation is finished by ALC1 bit = "0" or PMMIC bit = "0". * LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits When setting IPGA gain at the start of ALC1 operation, IPGA6-0 bits should be set while PMMIC bit is "1" and ALC1 bit is "0". When PMMIC bit = "1", IPGA6-0 bits value aren't reflected to IPGA. When ALC1 bit is changed from "1" to "0", IPGA holds the last gain value set automatically by ALC1 operation. Example: Limiter = Zero crossing Enable Recovery Cycle = 16ms @ fs= 8kHz Limiter and Recovery Step = 1 Maximum Gain = +27.5dB Limiter Detection Level = -4dBFS Manual Mode ALC2 bit = "1" (default) (1) Addr=06H, Data=00H WR (ZTM1-0, WTM1-0, LTM1-0) WR (REF6-0) (2) Addr=08H, Data=47H WR (IPGA6-0) * The value of IPGA should be the same or smaller than REF's (3) Addr=09H, Data=10H WR (ALC1= "1", LMAT1-0, RATT, LMTH, ZELM) (4) Addr=07H, Data=61H ALC1 Operation Note : WR : Write Figure 31. Registers set-up sequence at the ALC1 operation MS0396-E-00 - 33 - 2005/06 ASAHI KASEI [AK4632] Digital Output Volume The AK4632 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVOL7-0 bits. The volume is included in front of a DAC block, a input data of DAC is changed from +12 to -115dB with MUTE. This volume has a soft transition function. It takes 1061/fs or 256/fs from 00H to FFH. DVOL7-0 Gain 00H +12.0dB 01H +11.5dB 02H +11.0dB * * 18H 0dB Default * * FDH -114.5dB FEH -115.0dB FFH MUTE (-) Table 16. Digital Output Volume Code Table DVTM bit 0 1 The transition time from 00H to FFH of DVOL7-0 bits Transition Time fs=8kHz fs=22.05kHz 1061/fs 133msec 48msec 256/fs 32msec 12msec Table 17.Setting of transition time BEEP Input When the PMBP bit is set to "1", the beep input is powered-up. And when the BEEPS bit is set to "1", the input signal from the BEEP pin is output to Speaker-Amp. When the BEEPA bit is set to "1", the input signal from the BEEP pin is output to the mono line output amplifier. The external resister Ri adjusts the signal level of BEEP input. The gains are shown in Table 18, when Ri = 20k. These gain are in inverse proportion to Ri. Rf Ri BEEP + Figure 32. Block Diagram of BEEP pin SPKG1-0 bits 00 01 10 11 SPP/SPN Gain BEEP +7.89dB +9.93dB +14.11dB +16.15dB Table 18. Beep input gain at Ri = 20k BEEP AOUT Gain 0dB 0dB 0dB 0dB MS0396-E-00 - 34 - 2005/06 ASAHI KASEI [AK4632] MONO LINE OUTPUT (AOUT pin) A signal of DAC is output from AOUT pin. When the DACA bit is "0", this output is OFF. The load resistance is 10k(min). When PMAO bit is "0" and AOPSN bit is "0", the mono line output enters power-down and is pulled down by 100(typ). If PMAO bit is controlled at AOPSN bit = "1", POP noise will be reduced at power-up and down. Then, this line should be pulled down by 20k of resister after C-coupling shown in Figure 33. This rising and falling time is max 300 ms at C=1.0F . When PMAO bit is "1" and AOPSN bit is "0", the mono line output enters power-up state. 1F AOUT 220 20k Figure 33. AOUT external circuit in case of using POP Reduction function. AOUT Control Sequence in case of using POP Reduction Circuit (2 ) P M A O b it (1 ) A O P S N b it (3 ) (4 ) (6 ) (5 ) A O U T p in 300 m s N o r m a l O u tp u t 300 m s Figure 34. Mono Line Output Control Sequence in case of using POP Reduction function.. (1) Set AOPSN bit = "1". Mono line output enters the power-save mode. (2) Set PMAO bit = "1". Mono line output exits the power-down mode. AOUT pin rises up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1F. (3) Set AOPSN bit = "0" after AOUT pin rises up. Mono line output exits the power-save mode. Mono line output is enabled. (4) Set AOPSN bit = "1". Mono line output enters power-save mode. (5) Set PMAO bit = "1". Mono line output enters power-down mode. AOUT pin falls down to AVSS. Fall time is 200ms (max 300ms) at C=1F. (6) Set AOPSN bit = "0" after AOUT pin falls down. Mono line output exits the power-save mode. MS0396-E-00 - 35 - 2005/06 ASAHI KASEI [AK4632] Speaker Output The power supply voltage for Speaker-Amp SVDD can be set to from 2.6V to 5.25V. However, SVDD should be set to from 2.6V to 3.6V, when the load resistance is less than 50(ex. a dynamic speaker). The output signal from DAC is input to the Speaker-amp via the ALC2 circuit. This Speaker-amp is a mono output controlled by BTL and a gain of the Speaker-Amp is set by SPKG1-0 bit. In the case of ALC2 OFF, the output voltage depends on AVDD and SPKG1-0 bits. In the case of ALC2 ON, the output voltage depends on SVDD and SPKG1-0 bits. The output level of ALC2 is proportional to SVDD. SPKG1-0 bits Gain 00 0dB 01 +2.04dB 10 +6.22dB 11 +8.26dB (Note) These Gain from the level at SPKG1-0bits= "00". Table 19. Gain of Speaker-Amp at ALC2 OFF Output Voltage from Speaker-Amp Output Voltage from SPKG1-0 bits AVDD SVDD at ALC2 OFF and DAC Input=0dBFS Speaker-Amp at ALC ON 00 3.3V 3.3V 3.27Vpp, 167mW@8 3.09Vpp, 150mW@8 01 3.3V 3.3V 4.15Vpp, 269mW@8 3.92Vpp, 240mW@8 10 3.3V 3.3V 6.91Vpp (Note) Not Available 11 3.3V 3.3V 8.50Vpp (Note) Not Available 00 3.3V 5.0V 3.27Vpp Not Available 01 3.3V 5.0V 4.15Vpp Not Available 10 3.3V 5.0V 6.91Vpp 6.34Vpp 11 3.3V 5.0V 8.50Vpp 8.02Vpp (Note) This output voltage is assumed that the signal is not clipped. In actual, the signal will be clipped when DAC outputs 0dBFS signal. The output power is 400mW@8, SVDD=3.3V. Table 20. Speaker-Amp Output Voltage [Caution for using Piezo Speaker] When a piezo speaker (load capacitance > 30pF) is used, resistances more than 10 should be inserted between SPP/SPN pins and speaker in series, respectively, as shown in Figure 35. Zener diodes should be inserted between speaker and GND as shown in Figure 35, in order to protect SPK-Amp of AK4632 from the power that the piezo speaker outputs when the speaker is pressured. Zener diodes of the following Zener voltage should be used. 92% of SVDD Zener voltage of Zener diodo(ZD of Figure 35) SVDD+0.3V Ex) In case of SVDD = 5.0V : 4.6V ZD 5.3V For example, Zener diode which Zener voltage is 5.1V(Min :4.97V, Max 5.24V) can be used. MS0396-E-00 - 36 - 2005/06 ASAHI KASEI [AK4632] ZD SPK-Amp SPP 10 SPN 10 ZD Figure 35. Circuit of Speaker Output(Load Capacitance > 30pF) PMSPK bit SPPS bit SPP pin Hi-Z Hi-Z SPN pin Hi-Z SVDD/2 SVDD/2 Hi-Z >t1(Note) >0 Figure 36. Power-up/Power-down Timing for Speaker-Amp (Note) "t1" depends on the time constant of input resistance of MIN and capacitor between MOUT pin and MIN pin. If Speaker-Amp output is enabled before MIN-Amp (ALC2) becomes stable, pop noise may occur. Ex) C of MOUT pin - MIN pin = 0.1 F, Input resistance of MIN pin = 36k(Max) : t1 = 5 = 18ms C of MOUT pin - MIN pin and the Input resistance(Rin) of MIN pin compose of HPF which cut off frequency(fc) are the followings. fc = 66Hz@Rin=24k(typ), 133Hz@Rin=12k(min), 44Hz@Rin=36k(max) MS0396-E-00 - 37 - 2005/06 ASAHI KASEI [AK4632] SPK-ALC Operation The ALC (Automatic Level Control) operation of speaker output is done by ALC2 block when ALC2 bit is "1". Input resistance of the ALC2 is 24k (typ) and centered around VCOM voltage. The ALC2 level diagram is shown in Figure 37 ~Figure 40. The limiter detection level is proportional to SVDD voltage. The output level is limited by the ALC2 circuit when the input signal exceeds -7.1dBV (@SPKG1 bit = "0", SVDD=3.3V or @SPKG1 bit = "1", SVDD = 5V). When a continuous signal of -7.1dBV or greater is input to the ALC2 circuit, the change period of the ALC2 limiter operation is 250s (=2/fs@fs=8kHz) and the attenuation level is 0.5dB/step. The ALC2 recovery operation uses zero crossings and gains of 1dB/step. The ALC2 recovery operation is done until the input level of the Speaker-amp goes to -9.1dBV (@SPKG1 bit = "0", SVDD=3.3V or @SPKG1 bit = "1", SVDD = 5V). Maximum gain of the ALC2 recovery operation is set by RFS5-0 bits. When the input signal is between -9.1dBV and -7.1dBV, the ALC2 limiter or recovery operations are not done. When the PMSPK bit changes from "0" to "1", the initilization cycle (512/fs = 64ms @fs=8kHz at ROTM bit = "0") starts. The ALC2 is disabled (The ALC2 gain is fixed to "-3.5dB".) during the initilization cycle and the ALC2 starts from "-2dB" after completing the initilization cycle. The ROTM bit and RFS5-0 bits set during the PMSPK bit = "0". When the ALC2 is disable, a gain of the ALC2 block is fixed to -3.5dB. Therefore, a gain of internal speaker block is shown in Table 22. Parameter Operation Start Level Period fs=8kHz fs=16kHz ALC2 Limiter operation -5.2dBV 2/fs = 250s 2/fs = 125s No ALC2 Recovery operation -7.2dBV 512/fs=64ms 512/fs=32ms Yes (Timeout = Period Time) Zero-crossing Detection ATT/GAIN 0.5dB step 1dB step Table 21. Limiter /Recovery of ALC2 (ROTM bit = "0") SPKG1-0 bits Gain 00 +4.4dB 01 +6.4dB 10 +10.6dB 11 +12.7dB Table 22. Gain of Speaker-Amp at ALC2 OFF(Full-differential Output) MS0396-E-00 - 38 - 2005/06 ASAHI KASEI [AK4632] 0.8dBV -3.1dBV -3.1dBV -4.0dB -8dB +2.0dB -11.1dBV FS-6.0dB = -9.1dBV +6.0dB +14.0dB -8dB -23.1dBV +7.9dB FS-4.0dB = -7.1dBV 0dBV -1.2dBV +7.9dB -5.2dBV Full-differential Single-ended FS +1.9dB -10dBV FS-12dB -15.1dBV -15.1dBV -20dBV -30dBV DVOL DAC ALC2 SPK-AMP (AVDD=3.3V, SVDD=3.3V, DVOL=-8.0dB/0dB, SPKG1-0 bit = "00",) * FS = Full Scale Figure 37. Speaker-Amp Output Level Diagram 10dBV Full-differential 0.8dBV +9.9dB -3.2dBV -4.0dB -8dB +2.0dB -11.1dBV FS-6.0dB = -9.1dBV -15.1dBV -15.1dBV +6.0dB +14.0dB -8dB -23.1dBV +3.9dB 2.8dBV FS-4dB = -7.1dBV -3.1dBV -3.1dBV +9.9dB 0dBV Single-ended FS -10dBV FS-12dB -20dBV -30dBV DVOL DAC ALC2 SPK-AMP (AVDD=3.3V, SVDD=3.3V, DVOL=-8.0dB/0dB, SPKG1-0 bit = "01",) * FS = Full Scale Figure 38. Speaker-Amp Output Level Diagram MS0396-E-00 - 39 - 2005/06 ASAHI KASEI [AK4632] 10dBV 7.0dBV +14.1dB +14.1dB -3.1dBV -3.1dBV FS-4dB = -7.1dBV -4.0dB -8dB +2.0dB -11.1dBV FS-6.0dB = -9.1dBV -15.1dBV -15.1dBV +6.0dB +14.0dB -8dB -23.1dBV 5.0dBV 1.0dBV Full-differential Single-ended 0dBV FS +8.1dB -10dBV FS-12dB -20dBV -30dBV DVOL DAC ALC2 SPK-AMP (AVDD=3.3V, SVDD=5.0V, DVOL=-8.0dB/0dB, SPKG1-0 bit = "10",) * FS = Full Scale Figure 39. Speaker-Amp Output Level Diagram 10dBV 7.1dBV 3.1dBV 9.1dBV +16.2dB +16.2dB Full-differential Single-ended 0dBV -3.1dBV -3.1dBV FS -8dB FS-4dB = -7.1dBV -4.0dB +2.0dB +10.2dB -10dBV FS-6.0dB = -9.1dBV -11.1dBV FS-12dB -15.1dBV -15.1dBV +6.0dB +14.0dB -8dB -20dBV -23.1dBV -30dBV DVOL DAC ALC2 SPK-AMP (AVDD=3.3V, SVDD=5.0V, DVOL=-8.0dB/0dB, SPKG1-0 bit = "11",) * FS = Full Scale Figure 40. Speaker-Amp Output Level Diagram MS0396-E-00 - 40 - 2005/06 ASAHI KASEI [AK4632] Video Block Video-Amp has a drivability for a load resistance of 150. The AK4632 has a composite input and output. A Low Pass Filter(LPF) and Gain Control Amp(GCA) are integrated and both DC output and Sag Compensation circuit are supported as shown in Figure 41 and Figure 42. The capacitance for Sag Compensation circuit is 100 F+2.2 F or 47 F+1.0 F. When DC output is used, VOUT pin and VSAG pin must be shorted. The output clamp voltage is 150mV(typ) at DC output. SAGC1-0 bits and VVDD voltage should be set as shown in Table 23. Table 25 shows the gain and step of the gain control. The gain is set by VGCA4-0 bits. PMV bit controls the power up and down of the video block. VOUT pin outputs AVSS level at PMV bit = "1". YIN CLAMP LPF GCA -1dB ~ +10.5dB Step 0.5dB +6dB VOUT VSAG C1 75 C2 (C1=100 F, C2=2.2 F) or (C1=47 F, C2=1.0 F) Figure 41. Video block (using Sag Compensation circuit) YIN CLAMP LPF GCA -1dB ~ +10.5dB Step 0.5dB +6dB VOUT VSAG 75 Figure 42. Video block (at DC Output)) SAGC1 bit 0 0 1 1 SAGC0 bit VVDD voltage Output Circuit 0 DC output 2.8 V VVDD 3.6V 1 Not Available 0 Sag compensation 2.85V VVDD < 4.75V 1 Sag compensation 4.5 V VVDD < 5.25V Table 23. Setting of VVDD and video output circuit. Default VVDD voltage GCA setting 0dB 2.8 V VVDD 3.6V 0dB 3.135 V VVDD 5.25V -1dB (Note) 2.85V VVDD < 3.135 V 0dB Sag compensation 47 F+1.0 F 3.135 V VVDD 5.25V -1dB (Note) 2.85V VVDD < 3.135 V Note : When the sag compensation circuit is used at less than 3.135V of VVDD, the GCA should be set to -1dB in order to avoid clipping of output video signal. Note that the video will become dark at that time. Table 24. Gain compensation Output Circuit DC output Sag compensation 100 F+2.2 F MS0396-E-00 - 41 - 2005/06 ASAHI KASEI [AK4632] VGCA4-0 bits 17H 16H 15H : 04H 03H 02H 01H 00H GAIN(dB) +10.5dB +10.0dB +9.5dB : +1.0dB +0.5dB 0.0dB -0.5dB -1.0dB Table 25. Setting of GCA STEP 0.5dB Default Serial Control Interface Internal registers may be written by using the 3-wire P interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 2-bit Chip address (Fixed to "10"), Read/Write (Fixed to "1"), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. The clock speed of CCLK is 5MHz (max). The value of internal registers is initialized at PDN pin = "L". CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A2 A0 D7 D6 D5 D4 D3 D2 D1 D0 "1" "0" "1" C1-C0: R/W: A4-A0: D7-D0: Chip Address (C1 = "1", C0 = "0"); Fixed to "10" READ/WRITE ("1": WRITE, "0": READ); Fixed to "1" Register Address Control data Figure 43. Serial Control I/F Timing MS0396-E-00 - 42 - 2005/06 ASAHI KASEI [AK4632] Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Input PGA Control Digital Volume Control ALC2 Mode Control Video Mode Control D7 0 PMV SPPS 0 PLL3 0 DVTM 0 0 0 DVOL7 0 0 D6 PMVCM 0 BEEPS AOPSN PLL2 0 ROTM ALC2 REF6 IPGA6 DVOL6 0 SAGC1 D5 PMBP 0 ALC2S MGAIN1 PLL1 FS3 ZTM1 ALC1 REF5 IPGA5 DVOL5 RFS5 SAGC0 D4 PMSPK 0 DACA SPKG1 PLL0 MSBS ZTM0 ZELM REF4 IPGA4 DVOL4 RFS4 VGCA4 D3 PMAO M/S DACM SPKG0 BCKO1 BCKP WTM1 LMAT1 REF3 IPGA3 DVOL3 RFS3 VGCA3 D2 PMDAC MCKPD MPWR BEEPA BCKO0 FS2 WTM0 LMAT0 REF2 IPGA2 DVOL2 RFS2 VGCA2 D1 PMMIC MCKO MICAD ALC1M DIF1 FS1 LTM1 RATT REF1 IPGA1 DVOL1 RFS1 VGCA1 D0 PMADC PMPLL MGAIN0 ALC1A DIF0 FS0 LTM0 LMTH REF0 IPGA0 DVOL0 RFS0 VGCA0 The PDN pin = "L" resets the registers to their default values. Note: Unused bits must contain a "0" value. Note: Only write to address 00H to 0CH. MS0396-E-00 - 43 - 2005/06 ASAHI KASEI [AK4632] Register Definitions Addr 00H Register Name Power Management 1 Default D7 0 0 D6 PMVCM 0 D5 PMBP 0 D4 PMSPK 0 D3 PMAO 0 D2 PMDAC 0 D1 PMMIC 0 D0 PMADC 0 PMADC: ADC Block Power Control 0: Power down (Default) 1: Power up When the PMADC bit changes from "0" to "1", the initialization cycle (1059/fs=133ms@8kHz) starts. After initializing, digital data of the ADC is output. PMMIC: MIC In Block (MIC-Amp and ALC1) Power Control 0: Power down (Default) 1: Power up PMDAC: DAC Block Power Control 0: Power down (Default) 1: Power up PMAO: Mono Line Out Power Control 0: Power down (Default) 1: Power up PMSPK: Speaker Block Power Control 0: Power down (Default) 1: Power up PMBP: BEEP In Power Control 0: Power down (Default) 1: Power up Even if PMBP bit is "0", the path is still connected between BEEP and AOUT/SPK-Amp. BEEPS and BEEPA bits should be set to "0" to disconnect these paths. PMVCM: VCOM Block Power Control 0: Power down (Default) 1: Power up Each block can be powered-down respectively by writing "0" in each bit. When the PDN pin is "L", all blocks are powered-down. When PMPLL and MCKO bits and all bits in 00H address are "0", all blocks are powered-down. Though the IPGA resisters are initialized, the other registers remain unchanged. (refer to the IPGA6-0 bits description) When any of the blocks are powered-up, the PMVCM bit must be set to "1". When PMPLL and MCKO bits and all bits in 00H address are "0", PMVCM bit can write to "0". When BEEP signal is output from Speaker-Amp (Signal path: BEEP pin SPP/SPN pins) or Mono Lineout-Amp (Signal path: BEEP pin AOUT pin) only, the clocks may not be present. When ADC, DAC, ALC1 or ALC2 is in operation, the clocks must always be present. MS0396-E-00 - 44 - 2005/06 ASAHI KASEI [AK4632] Addr 01H Register Name Power Management 2 Default D7 PMV 0 D6 0 0 D5 0 0 D4 0 0 D3 M/S 0 D2 MCKPD 1 D1 MCKO 0 D0 PMPLL 0 PMPLL: PLL Block Power Control Select 0: PLL is Power down and External is selected. (Default) 1: PLL is Power up and PLL Mode is selected. MCKO: Master Clock Output Enable 0: "L" Output (Default) 1: 256fs Output MCKPD: MCKI pin pull down control 0: Master Clock input enable 1: Pull down by 25k (typ.) (Default) M/S: Select Master / Slave Mode 0: Slave Mode (Default) 1: Master Mode PMV: Video Block Power Control 0: Power down (Default) 1: Power up MS0396-E-00 - 45 - 2005/06 ASAHI KASEI [AK4632] Addr 02H Register Name Signal Select 1 Default D7 SPPS 0 D6 BEEPS 0 D5 ALC2S 0 D4 DACA 0 D3 DACM 0 D2 MPWR 0 D1 MICAD 0 D0 MGAIN0 1 MGAIN1-0 : 1st MIC-amp Gain control(See Table 26) MGAIN 1 bit is located at D6 bit of 03H MGAIN1 bit 0 0 1 1 MGAIN0 bit Input Gain 0 0dB 1 +20dB 0 +26dB 1 +32dB Table 26. Input Gain Default MICAD: Switch Control from MIC In to ADC. 0: OFF (Default) 1: ON When MICAD bit is "1", the ALC1 output signal is input to ADC. MPWR: Power Supply Control for Microphone 0: OFF (Default) 1: ON When PMMIC bit is "1", MPWR bit is enabled. DACM: Switch Control from DAC to mono amp. 0: OFF (Default) 1: ON When PMSPK bit is "1", DACM bit is enabled. When PMSPK bit is "0", MOUT pin is Hi-Z state. DACA: Switch Control from DAC to mono line amp 0: OFF (Default) 1: ON When PMAO bit is "1", DACA bit is enabled. When PMAO bit is "0", the AOUT pin is AVSS. ALC2S: ALC2 output to Speaker-Amp Enable 0: OFF (Default) 1: ON When ALC2S bit is "1", the ALC2 output signal is input to Speaker-Amp. BEEPS: BEEP pin to Speaker-Amp Enable 0: OFF (Default) 1: ON When BEEPS bit is "1", the beep signal is input to Speaker-Amp. SPPS: Speaker-amp Power-Save-Mode 0: Power Save Mode (Default) 1: Normal Operation When SPPS bit is "1", the Speaker-amp is in power-save-mode and the SPP pin becomes Hi-z and SPN pin is set to SVDD/2 voltage. When the PMSPK bit = "1", this bit is valid. After the PDN pin changes from "L" to "H", the PMSPK bit is "0", which powers down Speaker-amp. MS0396-E-00 - 46 - 2005/06 ASAHI KASEI [AK4632] Addr 03H Register Name Signal Select 2 Default D7 0 0 D6 0 0 D5 MGAIN1 0 D4 SPKG1 0 D3 SPKG0 0 D2 BEEPA 0 D1 ALC1M 0 D0 ALC1A 0 ALC1A: Switch Control from ALC1 output signal to mono line output amp. 0: OFF (Default) 1: ON When PMAO bit is "1", ALC1A bit is enabled. When PMAO bit is "0", the AOUT pin is AVSS. ALC1M: Switch Control from ALC1 output signal to mono amp. 0: OFF (Default) 1: ON When PMSPK bit is "1", ALC1M is enabled. When PMSPK bit is "0", the MOUT pin goes Hi-Z state. BEEPA: Switch Control from beep signal to mono line output amp. 0: OFF (Default) 1: ON When PMAO bit is "1", BEEPA is enabled. When PMAO bit is "0", the AOUT pin is AVSS. SPKG1-0: Select Speaker-Amp Output Gain (See Table 27) SPKG1-0 bits Gain 00 0dB 01 +2.2dB 10 +4.4dB 11 +8.7dB Table 27. Gain of Speaker-Amp MGAIN1: Mic-Amplifier Gain Control(See Table 26) ALC1M IPGA DACM ALC2S MIX ALC2 SPK DAC BEEPS BEEP ALC1A DACA AOUT BEEPA Figure 44. Speaker and Mono Lineout-Amps switch control MS0396-E-00 - 47 - 2005/06 ASAHI KASEI [AK4632] AOPSN: Mono Line Output Power-Save Mode 0: Normal Operation 1: Power-Save Mode (Default) Power-save mode is enable at AOPSN bit = "1". POP noise at power-up/down can be reduced by changing at AOPSN bit = "1". (See Figure 34) Addr 04H Register Name Mode Control 1 Default D7 PLL3 0 D6 PLL2 0 D5 PLL1 0 D4 PLL0 0 D3 BCKO1 0 D2 BCKO0 0 D1 DIF1 1 D0 DIF0 0 DIF1-0: Audio Interface Format (See Table 28) Mode 0 1 2 3 DIF1 bit 0 0 1 1 DIF0 bit 0 1 0 1 SDTO (ADC) SDTI (DAC) DSP Mode DSP Mode MSB justified LSB justified MSB justified MSB justified I2S compatible I2S compatible Table 28. Audio Interface Format BICK 16fs 32fs 32fs 32fs Figure See Table 34 Figure 27 Figure 28 Figure 29 Default BCKO1-0: Select BICK output frequency at Master Mode (See Table 29) Mode 0 1 2 3 BICK Output Frequency 0 0 16fs 0 1 32fs 1 0 64fs 1 1 N/A Table 29. BICK Output Frequency at Master Mode BCKO1 bit BCKO0 bit Default PLL3-0: Select input frequency at PLL mode (See Table 30) Mode 0 1 2 3 4 5 6 7 12 13 Others PLL3 bit 0 0 0 0 0 0 0 0 1 1 PLL Reference Input Clock Input Pin Frequency FCK pin 1fs BICK pin 16fs BICK pin 32fs BICK pin 64fs MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 13.5MHz MCKI pin 27MHz Others N/A Table 30. Setting of PLL Mode (*fs: Sampling Frequency) PLL2 bit 0 0 0 0 1 1 1 1 1 1 PLL1 bit 0 0 1 1 0 0 1 1 0 0 PLL0 bit 0 1 0 1 0 1 0 1 0 1 Default MS0396-E-00 - 48 - 2005/06 ASAHI KASEI [AK4632] Addr 05H Register Name Mode Control 2 Default D7 0 0 D6 0 0 D5 FS3 0 D4 MSBS 0 D3 BCKP 0 D2 FS2 0 D1 FS1 0 D0 FS0 0 FS3-0: Setting of Sampling Frequency (See Table 31 and Table 32) and MCKI Frequency (See Table 33) These bits are selected to sampling frequency at PLL mode and MCKI frequency at EXT mode. Mode 0 1 2 3 4 5 6 7 10 11 14 15 Others Sampling Frequency 8kHz Default 12kHz 16kHz 24kHz 7.35kHz 11.025kHz 14.7kHz 22.05kHz 32kHz 48kHz 29.4kHz 44.1kHz Others N/A Table 31. Setting of Sampling Frequency at PLL2 bit = "1" and PMPLL bit = "1" FS3 bit 0 0 0 0 0 0 0 0 1 1 1 1 FS2 bit 0 0 0 0 1 1 1 1 0 0 1 1 FS1 bit 0 0 1 1 0 0 1 1 1 1 1 1 FS0 bit 0 1 0 1 0 1 0 1 0 1 0 1 Mode 0 1 2 3 6 7 Others FS2 bit FS1 bit FS0 bit Sampling Frequency Range Don't care 0 0 Default 7.35kHz fs 8kHz Don't care 1 0 8kHz < fs 12kHz Don't care 0 1 12kHz < fs 16kHz Don't care 1 1 16kHz < fs 24kHz Don't care 0 1 24kHz < fs 32kHz Don't care 1 1 32kHz < fs 48kHz Others N/A Table 32. Setting of Sampling Frequency at PLL2 bit = "0" and PMPLL bit = "1" FS3 bit 0 0 0 0 1 1 Mode 0 1 2 3 MCKI Input Sampling Frequency Frequency Range Don't care 0 256fs 0 7.35kHz fs 48kHz Don't care 1 1024fs 0 7.35kHz < fs 13kHz Don't care 0 256fs 1 7.35kHz < fs 48kHz Don't care 1 512fs 1 7.35kHz < fs 26kHz Table 33. MCKI Frequency at EXT Slave Mode (PMPLL bit = "0", M/S bit = "0") FS3-2 bits FS1 bit FS0 bit Default BCKP, MSBS: "00" (Default) (See Table 34) MSBS bit BCKP bit Audio Interface Format 0 0 Figure 23 0 1 Figure 24 1 0 Figure 25 1 1 Figure 26 Table 34. Audio Interface Format in Mode 0 Default MS0396-E-00 - 49 - 2005/06 ASAHI KASEI [AK4632] Addr 06H Register Name Timer Select Default D7 DVTM 0 D6 ROTM 0 D5 ZTM1 0 D4 ZTM0 0 D3 WTM1 0 D2 WTM0 0 D1 LTM1 0 D0 LTM0 0 LTM1-0: ALC1 limiter operation period at zero crossing disable (ZELM bit = "1") (See Table 35) The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is done by the period specified by the LTM1-0 bits. Default is "00" (0.5/fs). ALC1 Limiter Operation Period 8kHz 16kHz 0 0 0.5/fs Default 63s 31s 0 1 1/fs 125s 63s 1 0 2/fs 250s 125s 1 1 4/fs 500s 250s Table 35. ALC1 Limiter Operation Period at zero crossing disable (ZELM bit="1") LTM1 bit LTM0 bit WTM1-0: ALC1 Recovery Waiting Period (See Table 36) A period of recovery operation when any limiter operation does not occur during the ALC1 operation. Default is "00" (128/fs). WTM1 bit 0 0 1 1 ALC1 Recovery Operation Waiting Period 8kHz 16kHz 0 128/fs 16ms 8ms 1 256/fs 32ms 16ms 0 512/fs 64ms 32ms 1 1024/fs 128ms 64ms Table 36. ALC1 Recovery Operation Waiting Period WTM0 bit Default ZTM1-0: ALC1 Zero crossing timeout Period (See Table 37) When the IPGA perform zero crossing or timeout, the IPGA value is changed by the P WRITE operation, ALC1 recovery operation or ALC1 limiter operation (ZELM bit = "0"). Default is "00" (128/fs). ZTM1 bit 0 0 1 1 ZTM0 bit Zero Crossing Timeout Period 8kHz 16kHz 0 128/fs 16ms 8ms 1 256/fs 32ms 16ms 0 512/fs 64ms 32ms 1 1024/fs 128ms 64ms Table 37. Zero Crossing Timeout Period Default ROTM: Period time for ALC2 Recovery operation, ALC2 Zero Crossing Timeout and ALC2 initializing cycle. 0: 512/fs (Default) 1: 1024/fs The ROTM bit is set during the PMSPK bit = "0". DVTM : Digital Volume Soft Transition Time Control 0: 1061/fs (Default) 1: 256/fs This is the time to FFH from 00H of DVOL7-0 bits. MS0396-E-00 - 50 - 2005/06 ASAHI KASEI [AK4632] Addr 07H Register Name ALC Mode Control 1 Default D7 0 0 D6 ALC2 1 D5 ALC1 0 D4 ZELM 0 D3 LMAT1 0 D2 LMAT0 0 D1 RATT 0 D0 LMTH 0 LMTH: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (See Table 38 ) The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about 2dB. Default is "0". LMTH bit 0 1 ALC1 Limiter Detection Level ALC1 Recovery Waiting Counter Reset Level ADC Input -6.0dBFS -6.0dBFS > ADC Input -8.0dBFS ADC Input -4.0dBFS -4.0dBFS > ADC Input -6.0dBFS Table 38. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level Default RATT: ALC1 Recovery GAIN Step (See Table 39) During the ALC1 recovery operation, the number of steps changed from the current IPGA value is set. For example, when the current IPGA value is 30H and RATT bit = "1" is set, the IPGA changes to 32H by the ALC1 recovery operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value exceeds the reference level (REF6-0 bits), the IPGA value does not increase. RATT bit GAIN STEP 0 1 Default 1 2 Table 39. ALC1 Recovery Gain Step Setting LMAT1-0: ALC1 Limiter ATT Step (See Table 40) During the ALC1 limiter operation, when IPGA output signal exceeds the ALC1 limiter detection level set by LMTH, the number of steps attenuated from the current IPGA value is set. For example, when the current IPGA value is 47H and the LMAT1-0 bits = "11", the IPGA transition to 43H when the ALC1 limiter operation starts, resulting in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation value exceeds IPGA = "00" (-8dB), it clips to "00". LMAT1 bit LMAT0 bit ATT STEP 0 0 1 0 1 2 1 0 3 1 1 4 Table 40. ALC1 Limiter ATT Step Setting Default ZELM: Enable zero crossing detection at ALC1 Limiter operation 0: Enable (Default) 1: Disable When the ZELM bit = "0", the IPGA of each L/R channel perform a zero crossing or timeout independently and the IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1 recovery operation. When the ZELM bit = "1", the IPGA value is changed immediately. MS0396-E-00 - 51 - 2005/06 ASAHI KASEI [AK4632] ALC1: ALC1 Enable 0: ALC1 Disable (Default) 1: ALC1 Enable When ALC1 bit is "1", the ALC1 operation is enabled. ALC2: ALC2 Enable 0: ALC2 Disable 1: ALC2 Enable (Default) After completing the initializing cycle (512/fs = 64ms @fs=8kHz at ROTM bit = "0"), the ALC2 operation is enabled. When the PMSPK bit changes from "0" to "1" or PDN pin changes from "L" to "H", the initilization cycle starts. Addr 08H Register Name ALC Mode Control 2 Default D7 0 0 D6 REF6 0 D5 REF5 1 D4 REF4 1 D3 REF3 0 D2 REF2 1 D1 REF1 1 D0 REF0 0 REF6-0: Reference value at ALC1 Recovery Operation (See Table 41) During the ALC1 recovery operation, if the IPGA value exceeds the setting reference value by gain operation, then the IPGA does not become larger than the reference value. For example, when REF7-0 = "30H", RATT = 2step, IPGA = 2FH, even if the input signal does not exceed the "ALC1 Recovery Waiting Counter Reset Level", the IPGA does not change to 2FH + 2step = 31H, and keeps 30H. Default is "36H". DATA (HEX) GAIN (dB) STEP 47 +27.5 46 +27.0 45 +26.5 : : 36 +19.0 Default : : 10 +0.0 : : 0.5dB 06 -5.0 05 -5.5 04 -6.0 03 -6.5 02 -7.0 01 -7.5 00 -8.0 Table 41. Setting Reference Value at ALC1 Recovery Operation MS0396-E-00 - 52 - 2005/06 ASAHI KASEI [AK4632] Addr 09H Register Name Input PGA Control Default D7 0 0 D6 IPGA6 0 D5 IPGA5 0 D4 IPGA4 1 D3 IPGA3 0 D2 IPGA2 0 D1 IPGA1 0 D0 IPGA0 0 IPGA6-0: Input Analog PGA (See Table 42) Default: "10H" (0dB) When IPGA gain is changed, IPGA6-0 bits should be written while PMMIC bit is "1" and ALC1 bit is "0". IPGA6-0 bits should be set at 2/fs(250s@fs=8kHz) after PMMIC bit is set to "1". IPGA gain is reset when PMMIC bit is "0", and then IPGA operation starts from the default value when PMMIC bit is changed to "1". When ALC1 bit is changed from "1" to "0", IPGA holds the last gain value set automatically by ALC1 operation. In a manual mode, IPGA can be set to any values in Table 42.The ZTM1-0 bits set zero crossing timeout period when IPGA value is changed. When the control register is written from the P, the zero crossing counter is reset and its counter starts. When the signal zero crossing or zero crossing timeout, the written value from the P becomes valid. DATA (HEX) GAIN (dB) STEP 47 +27.5 46 +27.0 45 +26.5 : : 36 +19.0 : : 10 +0.0 : : 0.5dB 06 -5.0 05 -5.5 04 -6.0 03 -6.5 02 -7.0 01 -7.5 00 -8.0 Table 42. Input Gain Setting Addr 0AH Register Name Digital Volume Control Default D7 DVOL7 0 D6 DVOL6 0 D5 DVOL5 0 D4 DVOL4 1 Default D3 DVOL3 1 D2 DVOL2 0 D1 DVOL1 0 D0 DVOL0 0 DVOL7-0: Output Digital Volume (See Table 43) The AK4632 has a digital output volume (256 levels, 0.5dB step, Mute). The gain can be set by the DVOL7-0 bits. The volume is included in front of a DAC block, a input data of DAC is changed from +12 to -115dB with MUTE. This volume has a soft transition function. It takes 1061/fs (=133ms @ fs = 8kHz) or 256/fs (=32ms @ fs = 8kHz) from 00H to FFH. Soft Transition Time is set by DVTM bit. DVOL7-0 Gain 00H +12.0dB 01H +11.5dB 02H +11.0dB * * 18H 0dB Default * * FDH -114.5dB FEH -115.0dB FFH MUTE (-) Table 43. Digital Volume Code Table MS0396-E-00 - 53 - 2005/06 ASAHI KASEI [AK4632] Addr 0BH Register Name ALC2 Mode Control Default D7 0 0 D6 0 0 D5 RFS5 1 D4 RFS4 1 D3 RFS3 1 D2 RFS2 1 D1 RFS1 0 D0 RFS0 0 RFS6-0: Reference value at ALC2 Recovery Operation (See Table 44) REFS5-0 bits Volume[dB] Step 3F +19.5 3E +19.0 3D +18.5 3C +18.0 Default : : 0.5dB 19 +0.5 18 +0.0 17 -0.5 : : 03 -10.5 02 -11.0 01 -11.5 00 -12.0 Table 44. Setting Reference Value at ALC2 Recovery Operation Addr 0CH Register Name Video Mode Control Default D7 0 0 D6 SAGC1 0 D5 SAGC0 0 D4 VGCA4 0 D3 VGCA3 0 D2 VGCA2 0 D1 VGCA1 1 D0 VGCA0 0 VGCA4-0: Gain Control of Video output(See Table 25) SAGC1-0: Select Video Output Circuit (See Table 23) MS0396-E-00 - 54 - 2005/06 ASAHI KASEI [AK4632] SYSTEM DESIGN Figure 45 shows the system connection diagram. An evaluation board [AKD4632] is available which demonstrates the optimum layout, power supply arrangements and measurement results. C 2.2k 10 0.1 VCOM 32 MIC 30 MICOUT 29 AIN 28 BEEP 27 AOUT 26 MPI 31 1 0.22 R 20k 220 1 MOUT 25 0.1 Cp Rp 1 VCOC MIN 24 SVSS 23 SVDD 22 Analog Supply 2.63.6V Analog Supply 2.85.25V 0.1 10 + R2 Speaker + 10 10 + 0.1 0.1 0.1u 2 AVDD 3 AVSS 4 VVDD 5 VIN 6 VOUT Analog Supply 2.65.25V Top View SPP 21 SPN 20 MCKO 19 MCKI 18 R1 75 Cv Cs 7 VSAG 13 SDTO 10 CCLK 11 CDTI 15 BICK 12 SDTI 16 DVDD 8 PDN 9 CSN ZD2 ZD1 Dynamic SPK : R1,R2 : Short ZD1,ZD2 : Open Peizo SPK : R1,R2 : 10 ZD1,ZD2 : Required 14 FCK SAGC1-0 bits = "00" Cv : Short Cs : Short SAGC1-0 bits = "10" or "11" Cv=100F & Cs=2.2F or Cv=47F & Cs=1.0F DVSS 17 10 0.1 + 10 DSP or P Figure 45. Typical Connection Diagram Notes: - AVSS, DVSS and SVSS of the AK4632 should be distributed separately from the ground of external controllers. - The exposed pad on the bottom surface of the package must be open. - All digital input pins except pull-down pin should not be left floating. - Value of R and C of BEEP pin should depend on system. - When the AK4632 is EXT mode (PMPLL bit = "0"), a resistor and capacitor of VCOC pin is not needed. - When the AK4632 is PLL mode (PMPLL bit = "1"), a resistor and capacitor of VCOC pin is shown in Table 45. - Input resistance of AIN pin and Capacitance between MICOUT pin and AIN pin compose of HPF. When the capacitance is 0.22F, the cut off frequency is typ.72Hz(typ)(min. 48Hz, max. 145Hz). Mode PLL3 bit 0 0 0 0 0 0 0 0 1 1 PLL2 bit 0 0 0 0 1 1 1 1 1 1 Others PLL1 bit 0 0 1 1 0 0 1 1 0 0 PLL0 bit 0 1 0 1 0 1 0 1 0 1 PLL Reference Clock Input Pin Input Frequency 0 1 2 3 4 5 6 7 12 13 Others FCK pin 1fs BICK pin 16fs BICK pin 32fs BICK pin 64fs MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 13.5MHz MCKI pin 27MHz N/A Table 45. Setting of PLL Mode (*fs: Sampling Frequency) Rp and Cp of VCOC pin Rp[] Cp[F] 6.8k 220n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 10n 10k 10n PLL Lock Time (max) 160ms 2ms 2ms 2ms 40ms 40ms 40ms 40ms 40ms 40ms Default MS0396-E-00 - 55 - 2005/06 ASAHI KASEI [AK4632] 1. Grounding and Power Supply Decoupling The AK4632 requires careful attention to power supply and grounding arrangements. AVDD, DVDD, SVDD and VVDD are usually supplied from the system's analog supply. If AVDD, DVDD, SVDD and VVDD are supplied separately, the correct power up sequence should be observed. AVSS, DVSS and SVSS of the AK4632 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4632 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference VCOM is a signal ground of this chip. A 2.2F electrolytic capacitor in parallel with a 0.1F ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4632. 3. Analog Inputs The Mic and Beep inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp for the Mic input and 0.6 x AVDD Vpp for the Beep input, centered around the internal common voltage (approx. 0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2RC). The AK4632 can accept input voltages from AVSS to AVDD. 4. Analog Outputs The input data format for the DAC is 2's complement. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). Mono output from the MOUT pin and Mono Line Output from the AOUT pin are centered at 0.45 x AVDD (typ). The Speaker-Amp output is centered at SVDD/2. MS0396-E-00 - 56 - 2005/06 ASAHI KASEI [AK4632] CONTROL SEQUENCE Clock Set up When ADC, DAC, ALC1, ALC2 and IPGA are used, the clocks must be supplied. 1. In case of PLL Master Mode. Power Supply Example: (1) PDN pin (2) (3) PMVCM bit (Addr:00H, D6) (4) Audio I/F Format: DSP Mode, BCKP = MSBS = "0" BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO : Enable Sampling Frequency:8kHz MCKPD bit (Addr:01H, D2) (5) (1) Power Supply & PDN pin = "L" "H" MCKO bit (Addr:01H, D1) PMPLL bit (Addr:01H, D0) (6) (2)Addr:01H, Data:0CH Addr:04H, Data:48H Addr:05H, Data:00H Input MCKI pin M/S bit (Addr:01H, D3) 40msec(max) (7) (3)Addr:00H, Data:40H (4)Addr:01H, Data:0BH Output BICK pin FCK pin (8) 1msec (max) MCKO, BICK and FCK output 40msec(max) (10) MCKO pin (9) Output Figure 46. Clock Set Up Sequence (1) MS0396-E-00 - 57 - 2005/06 ASAHI KASEI [AK4632] 2. When the external clocks (FCK or BICK pin) are used in PLL Slave Mode. Example: Power Supply (1) PDN pin (2) (3) Audio I/F Format : DSP Mode, BCKP = MSBS = "0" PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz PMVCM bit (Addr:00H, D6) 4fs ofPower Supply & PDN pin = "L" (1) "H" MCKPD bit (Addr:01H, D2) (4) "H" (2) Addr:04H, Data:30H Addr:05H, Data:00H PMPLL bit (Addr:01H, D0) (3) Addr:00H, Data:40H FCK pin BICK pin Internal Clock (6) Input (5) (4) Addr:01H, Data:05H BICK and FCK input Figure 47. Clock Set Up Sequence (2) MS0396-E-00 - 58 - 2005/06 ASAHI KASEI [AK4632] 3. When the external clock (MCKI pin) is used in PLL Slave Mode. Example: Power Supply (1) PDN pin (2) (3) Audio I/F Format: DSP Mode, BCKP = MSBS = "0" BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO : Enable Sampling Frequency:8kHz PMVCM bit (Addr:00H, D6) (4) (1) Power Supply & PDN pin = "L" "H" MCKPD bit (Addr:01H, D2) (5) MCKO bit (Addr:01H, D1) (2)Addr:01H, Data:04H Addr:04H, Data:48H Addr:05H, Data:00H PMPLL bit (Addr:01H, D0) (6) (3)Addr:00H, Data:40H Input 40msec(max) (7) MCKI pin (4)Addr:01H, Data:03H Output (9) MCKO pin (8) MCKO output start BICK pin FCK pin Input BICK and FCK input start Figure 48. Clock Set Up Sequence (3) MS0396-E-00 - 59 - 2005/06 ASAHI KASEI [AK4632] 4. EXT Slave Mode Example Power Supply (1) Audio I/F Format:MSB justified (ADC and DAC) Input MCKI frequency: 1024fs Sampling Frequency:8kHz MCKO: Disable PDN pin (2) (3) (1) Power Supply & PDN pin = "L" "H" PMVCM bit (Addr:00H, D6) MCKPD bit (Addr:01H, D2) (4) (2) Addr:04H, Data:02H Addr:05H, Data:01H PMPLL bit (Addr:01H, D0) "L" (5) (3) Addr:00H, Data:40H MCKI pin (5) Input (4) Addr:01H, Data:00H FCK pin BICK pin Input MCKI, BICK and FCK input Figure 49. Clock Set Up Sequence (4) MS0396-E-00 - 60 - 2005/06 ASAHI KASEI [AK4632] MIC Input Recording Example: FS3-0 bits (Addr:05H, D5,D2-0) XXXX (1) XXX PLL Master Mode Audio I/F Format:DSP Mode, BCKP=MSBS="0" Sampling Frequency:8kHz Pre MIC AMP:+20dB MIC Power On ALC1 setting:Refer to Figrure 29 ALC2 bit="1"(default) MIC Control (Addr:02H, D2-0) 001 (2) X1X 00H (3) (1) Addr:05H, Data:00H ALC1 Control 1 (Addr:06H) XXH XXH (4) (2) Addr:02H, Data:07H ALC1 Control 2 (Addr:08H) 47H (3) Addr:06H, Data:00H ALC1 Control 3 (Addr:07H) XXH (5) 61H or 21H ALC1 Enable ALC1 Disable (4) Addr:08H, Data:47H ALC1 State PMADC bit (Addr:00H, D0) ALC1 Disable (5) Addr:07H, Data:61H (6) Addr:00H, Data:43H (6) (7) 1059 / fs PMMIC bit (Addr:00H, D1) Recording ADC Internal State Power Down Initialize Normal State Power Down (7) Addr:00H, Data:40H Figure 50. MIC Input Recording Sequence MS0396-E-00 - 61 - 2005/06 ASAHI KASEI [AK4632] Speaker-amp Output Example: PLL, Master Mode Audio I/F Format :DSP Mode, BCKP=MSBS= "0" Sampling Frequency: 8kHz Digital Volume: -8dB ALC2 : Enable FS2-0 bits (Addr:05H, D5, D2-0) XXXX (1) XXXX (8) DACM bit (Addr:02H, D3) (2) (1) Addr:05H, Data:00H ALC2S bit (Addr:02H, D5) (2) Addr:02H, Data:28H ALC2 bit (Addr:07H, D6) 0 (3) X XXXXXXX (4) (9) (3) Addr:07H, Data:40H DVOL7-0 bits (Addr:0AH, D7-0) 0001100 (4) Addr:0AH, Data:28H PMDAC bit (Addr:00H, D2) (5) (5) Addr:00H, Data:54H PMSPK bit (Addr:00H, D4) (6) (6) Addr:02H, Data:A8H SPPS bit (Addr:02H, D7) (7) Playback SPP pin SPN pin Hi-Z Hi-Z SVDD/2 Normal Output Normal Output Hi-Z SVDD/2 Hi-Z (7) Addr:02H, Data:28H (8) Addr:00H, Data:40H Figure 51. Speaker-Amp Output Sequence MS0396-E-00 - 62 - 2005/06 ASAHI KASEI [AK4632] BEEP signal output from Speaker-Amp CLOCK ALC2 bit (Addr:07H, D6) Clocks can be stopped. Example: (1) Addr:07H, Data:00H 0 or 1 (1) 0 PMBP bit (Addr:00H, D2) (2) (6) (2) Addr:00H, Data:70H PMSPK bit (Addr:00H, D4) (3) Addr:02H, Data:60H ALC2S bit (Addr:02H, D5) 0 or 1 (3) 0 (7) (4) Addr:02H, Data:E0H BEEPS bit (Addr:02H, D6) (4) BEEP Signal Output SPPS bit (Addr:02H, D7) (5) (5) Addr:02H, Data:60H SPP pin SPN pin Hi-Z Hi-Z SVDD/2 Normal Output Normal Output Hi-Z (6) Addr:00H, Data:40H SVDD/2 Hi-Z (7) Addr:02H, Data:00H Figure 52. "BEPP-Amp Speaker-Amp" Output Sequence MS0396-E-00 - 63 - 2005/06 ASAHI KASEI [AK4632] MONO LINEOUT 1. In case of using an external mute circuit.(Compatible with AK4536/AK4630) Example: PLL, Master Mode Audio I/F Format :DSP Mode, BCKP=MSBS= "0" Sampling Frequency: 8kHz Digital Volume: -8dB FS3-0 bits (Addr:05H, D5,D2-0) XXXX (1) XXXX (1) Addr:05H, Data:00H (6) (2) (3) DACA bit (Addr:02H, D4) (2) Addr:02H, Data:10H DVOL7-0 bits (Addr:0AH, D7-0) 00011000 XXXXXXX (3) Addr:0AH, Data:28H PMDAC bit (Addr:00H, D2) (4) (5) (4) Addr:00H, Data:4CH PMAO bit (Addr:00H, D3) Playback AOUT pin Hi-Z Normal Output Hi-Z (5) Addr:00H, Data:40H (6) Addr:02H, Data:00H Figure 53. Mono Lineout Sequence MS0396-E-00 - 64 - 2005/06 ASAHI KASEI [AK4632] 2. In case of using POP reduction circuit of AK4632. Example: PLL, Master Mode Audio I/F Format :DSP Mode, BCKP=MSBS= "0" Sampling Frequency: 8kHz Digital Volume: -8dB MGAIN1=SPKG1=SPKG0=BEEPA=ALC1M =ALC1A= "0" (1) Addr:05H, Data:00H (2) Addr:02H, Data:10H FS2-0 bits (Addr:05H, D5,D2-0) XXXX (1) XXXX (9) (3) Addr:0AH, Data:28H (4) Addr:03H, Data:40H DACA bit (Addr:02H, D4) (2) (3) (5) Addr:00H, Data:4CH XXXXXXX DVOL7-0 bits (Addr:0AH, D7-0) 00011000 (6) Addr:03H, Data:00H PSAON bit (Addr:03H, D6) (4) (6) (7) (10) Playback (7) Addr:03H, Data:40H PMDAC bit (Addr:00H, D2) (5) >300 ms >300 ms (8) PMAO bit (Addr:00H, D3) (8) Addr:00H, Data:40H Normal Output AOUT pin (9) Addr:02H, Data:00H (10) Addr:03H, Data:00H Figure 54. Mono Lineout Sequence MS0396-E-00 - 65 - 2005/06 ASAHI KASEI [AK4632] Video Signal Input and Output Clocks PMVCM bit (Addr:00H, D6) SAGC1-0 bits (Addr:0CH, D6-5) VGCA4-0 bits (Addr:0CH, D4-0) PMV bit (Addr:01H, D7) Clocks can be stopped, if only video output is enable. Example: Audio Function :No use PLL Master Mode VIDEO Output : DC Output VGCA : 0dB X (1) XX (2) 1 (1) Addr:00H, Data:45H XX (2) Addr:0CH, Data:02H XXXXX (3) XXXXX (4) (3) Addr:01H, Data:8BH Video Output VOUT pin AVSS Normal Output AVSS (4) Addr:01H, Data:0BH Figure 55. Video Output Sequence MS0396-E-00 - 66 - 2005/06 ASAHI KASEI [AK4632] Stop of Clock Master clock can be stopped when ADC, DAC, ALC1, ALC2 and IPGA don't operate. 1. In case of PLL Master Mode Example: (1) PMPLL bit (Addr:01H,D0) (2) Audio I/F Format: DSP Mode, BCKP = MSBS = "0" BICK frequency at Master Mode : 64fs Input Master Clock Select at PLL Mode : 11.2896MHz Sampling Frequency:8kHz MCKO bit (Addr:01H,D1) "H" or "L" (3) (1) (2) (3) Addr:01H, Data:0CH Stop an external MCKI (4) MCKPD bit (Addr:01H,D2) External MCKI Input Figure 56. Clock Stopping Sequence (1) Example (1) PMPLL bit (Addr:01H,D0) (2) Audio I/F Format : DSP Mode, BCKP = MSBS = "0" PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz External BICK External FCK Input (2) (1) Addr:01H, Data:04H Input (2) Stop the external clocks Figure 57. Clock Stopping Sequence (2) MS0396-E-00 - 67 - 2005/06 ASAHI KASEI [AK4632] 3. When an external clock (MCKI pin) is used in PLL Slave Mode. (1) PMPLL bit (Addr:01H,D0) (1) MCKO bit (Addr:01H,D1) (1) Example Audio I/F Format : DSP Mode, BCKP = MSBS = "0" PLL Reference clock: MCKI BICK frequency: 64fs Sampling Frequency: 8kHz MCKPD bit (Addr:01H,D2) (2) (1) Addr:01H, Data:04H External MCKI Input (2) Stop the external clocks Figure 58. Clock Stopping Sequence (3) Example (1) MCKPD bit (Addr:01H,D2) (2) Audio I/F Format :MSB justified(ADC and DAC) Input MCKI frequency:1024fs Sampling Frequency:8kHz External MCKI External BICK External FCK Input (2) (1) Addr:01H, Data:04H Input (2) (2) Stop the external clocks Input Figure 59. Clock Stopping Sequence (4) Power down If the clocks are supplied, power down VCOM (PMVCM bit: "1" "0") after all blocks except for VCOM are powered-down and a master clock stops. The AK4632 is also powered-down by PDN pin = "L". When PDN pin = "L", the registers are initialized. MS0396-E-00 - 68 - 2005/06 ASAHI KASEI [AK4632] PACKAGE 32pin QFN (Unit: mm) 5.00 0.10 4.75 0.10 24 25 5.00 0.10 4.75 0.10 17 16 0.40 0.10 B 3.5 32 1 A 9 8 0.50 C0.42 Exposed Pad 32 1 3.5 0.23 +0.07 -0.05 C 0.08 C Note) The exposed pad on the bottom surface of the package must be open. Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0396-E-00 - 69 - 0.04 0.01+ 0.01 - 0.20 0.85 0.05 0.10 M AB 2005/06 ASAHI KASEI [AK4632] MARKING 4632 XXXX 1 XXXX : Date code identifier (4 digits) Revision History Date (YY/MM/DD) 05/06/01 Revision 00 Reason First Edition Page Contents IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0396-E-00 - 70 - 2005/06 |
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